# Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs

arXiv: https://arxiv.org/abs/2005.01574 · HTML: https://mlsanity.com/paper/2005.01574/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 29 Apr 2020.

## Built on by (most cited first, 2 of 2)

- [Deep Bidirectional Transformers for SoC Flow Specification Mining](https://mlsanity.com/paper/2203.13182/) (2022)
- [Mining SoC Message Flows with Attention Model](https://mlsanity.com/paper/2209.07929/) (2022)

## Abstract (arXiv)

Comprehensive specifications are essential for various activities across the entire validation continuum for system-on-chip (SoC) designs. However, specifications are often ambiguous, incomplete, or even contain inconsistencies or errors. This paper addresses this problem by developing a specification mining approach that automatically extracts sequential patterns from SoC transaction-level traces such that the mined patterns collectively characterize system-level specifications for SoC designs. This approach exploits long short-term memory (LSTM) networks trained with the collected SoC execution traces to capture sequential dependencies among various communication events. Then, a novel algorithm is developed to efficiently extract sequential patterns on system-level communications from the trained LSTM models. Several trace processing techniques are also proposed to enhance the mining performance. We evaluate the proposed approach on simulation traces of a non-trivial multi-core SoC prototype. Initial results show that the proposed approach is capable of extracting various patterns on system-level specifications from the highly concurrent SoC execution traces.