# ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems

arXiv: https://arxiv.org/abs/2004.10502 · HTML: https://mlsanity.com/paper/2004.10502/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 22 Apr 2020.

## Built on by (most cited first, 2 of 2)

- [AxOCS: Scaling FPGA-based Approximate Operators using Configuration Supersampling](https://mlsanity.com/paper/2309.12830/) (2023)
- [AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming](https://mlsanity.com/paper/2309.13445/) (2023)

## Abstract (arXiv)

There has been abundant research on the development of Approximate Circuits (ACs) for ASICs. However, previous studies have illustrated that ASIC-based ACs offer asymmetrical gains in FPGA-based accelerators. Therefore, an AC that might be pareto-optimal for ASICs might not be pareto-optimal for FPGAs. In this work, we present the ApproxFPGAs methodology that uses machine learning models to reduce the exploration time for analyzing the state-of-the-art ASIC-based ACs to determine the set of pareto-optimal FPGA-based ACs. We also perform a case-study to illustrate the benefits obtained by deploying these pareto-optimal FPGA-based ACs in a state-of-the-art automation framework to systematically generate pareto-optimal approximate accelerators that can be deployed in FPGA-based systems to achieve high performance or low-power consumption.