# Predictable Accelerator Design with Time-Sensitive Affine Types

arXiv: https://arxiv.org/abs/2004.04852 · HTML: https://mlsanity.com/paper/2004.04852/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 9 Apr 2020.

## Built on by (most cited first, 4 of 4)

- [Allo: A Programming Model for Composable Accelerator Design](https://mlsanity.com/paper/2404.04815/) (2024)
- [Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks](https://mlsanity.com/paper/2111.08848/) (2021)
- [QiMeng: Fully Automated Hardware and Software Design for Processor Chip](https://mlsanity.com/paper/2506.05007/) (2025)
- [From Pragmas to Partners: A Symbiotic Evolution of Agentic High-Level Synthesis](https://mlsanity.com/paper/2602.01401/) (2026)

## Abstract (arXiv)

Field-programmable gate arrays (FPGAs) provide an opportunity to co-design applications with hardware accelerators, yet they remain difficult to program. High-level synthesis (HLS) tools promise to raise the level of abstraction by compiling C or C++ to accelerator designs. Repurposing legacy software languages, however, requires complex heuristics to map imperative code onto hardware structures. We find that the black-box heuristics in HLS can be unpredictable: changing parameters in the program that should improve performance can counterintuitively yield slower and larger designs. This paper proposes a type system that restricts HLS to programs that can predictably compile to hardware accelerators. The key idea is to model consumable hardware resources with a time-sensitive affine type system that prevents simultaneous uses of the same hardware structure. We implement the type system in Dahlia, a language that compiles to HLS C++, and show that it can reduce the size of HLS parameter spaces while accepting Pareto-optimal designs.