# Workload-Aware DRAM Error Prediction using Machine Learning

arXiv: https://arxiv.org/abs/2003.12448 · HTML: https://mlsanity.com/paper/2003.12448/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 17 Mar 2020.

## Built on by (most cited first, 4 of 4)

- [DRAM Failure Prediction in AIOps: Empirical Evaluation, Challenges and Opportunities](https://mlsanity.com/paper/2104.15052/) (2021)
- [Exploring Error Bits for Memory Failure Prediction: An In-Depth Correlative Study](https://mlsanity.com/paper/2312.02855/) (2023)
- [Investigating Memory Failure Prediction Across CPU Architectures](https://mlsanity.com/paper/2406.05354/) (2024)
- [Reinforcement Learning-based Adaptive Mitigation of Uncorrected DRAM Errors in the Field](https://mlsanity.com/paper/2407.16377/) (2024)

## Abstract (arXiv)

The aggressive scaling of technology may have helped to meet the growing demand for higher memory capacity and density, but has also made DRAM cells more prone to errors. Such a reality triggered a lot of interest in modeling DRAM behavior for either predicting the errors in advance or for adjusting DRAM circuit parameters to achieve a better trade-off between energy efficiency and reliability. Existing modeling efforts may have studied the impact of few operating parameters and temperature on DRAM reliability using custom FPGAs setups, however they neglected the combined effect of workload-specific features that can be systematically investigated only on a real system. In this paper, we present the results of our study on workload-dependent DRAM error behavior within a real server considering various operating parameters, such as the refresh rate, voltage and temperature. We show that the rate of single- and multi-bit errors may vary across workloads by 8x, indicating that program inherent features can affect DRAM reliability significantly. Based on this observation, we extract 249 features, such as the memory access rate, the rate of cache misses, the memory reuse time and data entropy, from various compute-intensive, caching and analytics benchmarks. We apply several supervised learning methods to construct the DRAM error behavior model for 72 server-grade DRAM chips using the memory operating parameters and extracted program inherent features. Our results show that, with an appropriate choice of program features and supervised learning method, the rate of single- and multi-bit errors can be predicted for a specific DRAM module with an average error of less than 10.5 %, as opposed to the 2.9x estimation error obtained for a conventional workload-unaware error model.