# DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training

arXiv: https://arxiv.org/abs/2003.06471 · HTML: https://mlsanity.com/paper/2003.06471/

## Key facts

- Cited by 33 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 13 Mar 2020.

## Built on by (most cited first, 30 of 33)

- [A flexible and fast PyTorch toolkit for simulating training and inference on analog crossbar arrays](https://mlsanity.com/paper/2104.02184/) (2021)
- [Bottom-up and top-down approaches for the design of neuromorphic processing systems: Tradeoffs and synergies between natural and artificial intelligence](https://mlsanity.com/paper/2106.01288/) (2021)
- [Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inference](https://mlsanity.com/paper/2307.09357/) (2023)
- [Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computing](https://mlsanity.com/paper/2305.18416/) (2023)
- [LLS: Local Learning Rule for Deep Neural Networks Inspired by Neural Activity Synchronization](https://mlsanity.com/paper/2405.15868/) (2024)
- [ClipFormer: Key-Value Clipping of Transformers on Memristive Crossbars for Write Noise Mitigation](https://mlsanity.com/paper/2402.02586/) (2024)
- [Binary Weight Multi-Bit Activation Quantization for Compute-in-Memory CNN Accelerators](https://mlsanity.com/paper/2508.21524/) (2025)
- [CHIME: Chiplet-based Heterogeneous Near-Memory Acceleration for Edge Multimodal LLM Inference](https://mlsanity.com/paper/2601.19908/) (2025)
- [FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators](https://mlsanity.com/paper/2401.10522/) (2024)
- [H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations](https://mlsanity.com/paper/2404.04173/) (2024)
- [TReX- Reusing Vision Transformer's Attention for Efficient Xbar-based Computing](https://mlsanity.com/paper/2408.12742/) (2024)
- [Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimization](https://mlsanity.com/paper/2410.16759/) (2024)
- [Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures](https://mlsanity.com/paper/2501.09588/) (2025)
- [Low-Rank Compression for IMC Arrays](https://mlsanity.com/paper/2502.07820/) (2025)
- [NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities](https://mlsanity.com/paper/2505.02314/) (2025)
- [Design Space Exploration of Dense and Sparse Mapping Schemes for RRAM Architectures](https://mlsanity.com/paper/2201.06703/) (2022)
- [HeTraX: Energy Efficient 3D Heterogeneous Manycore Architecture for Transformer Acceleration](https://mlsanity.com/paper/2408.03397/) (2024)
- [MEMHD: Memory-Efficient Multi-Centroid Hyperdimensional Computing for Fully-Utilized In-Memory Computing Architectures](https://mlsanity.com/paper/2502.07834/) (2025)
- [Regularization-based Framework for Quantization-, Fault- and Variability-Aware Training](https://mlsanity.com/paper/2503.01297/) (2025)
- [Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computing](https://mlsanity.com/paper/2506.00004/) (2025)
- [CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Search](https://mlsanity.com/paper/2509.25862/) (2025)
- [Making Analog Training Scale: Co-Designing Mapping, Optimizer, and Converters](https://mlsanity.com/paper/2609.36584/) (2026)
- [SEMULATOR: Emulating the Dynamics of Crossbar Array-based Analog Neural System with Regression Neural Networks](https://mlsanity.com/paper/2101.07864/) (2021)
- [CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials](https://mlsanity.com/paper/2306.14649/) (2023)
- [Towards Efficient Hyperdimensional Computing Using Photonics](https://mlsanity.com/paper/2311.17801/) (2023)
- [Mem-elements based Neuromorphic Hardware for Neural Network Application](https://mlsanity.com/paper/2403.03002/) (2024)
- [Low-power Spike-based Wearable Analytics on RRAM Crossbars](https://mlsanity.com/paper/2502.06736/) (2025)
- [Row-Column Hybrid Grouping for Fault-Resilient Multi-Bit Weight Representation on IMC Arrays](https://mlsanity.com/paper/2508.15685/) (2025)
- [HePGA: A Heterogeneous Processing-in-Memory based GNN Training Accelerator](https://mlsanity.com/paper/2508.16011/) (2025)
- [Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators](https://mlsanity.com/paper/2603.03880/) (2026)

## Abstract (arXiv)

DNN+NeuroSim is an integrated framework to benchmark compute-in-memory (CIM) accelerators for deep neural networks, with hierarchical design options from device-level, to circuit-level and up to algorithm-level. A python wrapper is developed to interface NeuroSim with a popular machine learning platform: Pytorch, to support flexible network structures. The framework provides automatic algorithm-to-hardware mapping, and evaluates chip-level area, energy efficiency and throughput for training or inference, as well as training/inference accuracy with hardware constraints. Our prior work (DNN+NeuroSim V1.1) was developed to estimate the impact of reliability in synaptic devices, and analog-to-digital converter (ADC) quantization loss on the accuracy and hardware performance of inference engines. In this work, we further investigated the impact of the analog emerging non-volatile memory non-ideal device properties for on-chip training. By introducing the nonlinearity, asymmetry, device-to-device and cycle-to-cycle variation of weight update into the python wrapper, and peripheral circuits for error/weight gradient computation in NeuroSim core, we benchmarked CIM accelerators based on state-of-the-art SRAM and eNVM devices for VGG-8 on CIFAR-10 dataset, revealing the crucial specs of synaptic devices for on-chip training. The proposed DNN+NeuroSim V2.0 framework is available on GitHub.