# A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification

arXiv: https://arxiv.org/abs/2003.06310 · HTML: https://mlsanity.com/paper/2003.06310/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 12 Mar 2020.

## Built on by (most cited first, 1 of 1)

- [SpikeFit: Towards Optimal Deployment of Spiking Networks on Neuromorphic Hardware](https://mlsanity.com/paper/2510.15542/) (2025)

## Abstract (arXiv)

Neural network hardware is considered an essential part of future edge devices. In this paper, we propose a binary-weight spiking neural network (BW-SNN) hardware architecture for low-power real-time object classification on edge platforms. This design stores a full neural network on-chip, and hence requires no off-chip bandwidth. The proposed systolic array maximizes data reuse for a typical convolutional layer. A 5-layer convolutional BW-SNN hardware is implemented in 90nm CMOS. Compared with state-of-the-art designs, the area cost and energy per classification are reduced by 7× and 23×, respectively, while also achieving a higher accuracy on the MNIST benchmark. This is also a pioneering SNN hardware architecture that supports advanced CNN architectures.