# MC2RAM: Markov Chain Monte Carlo Sampling in SRAM for Fast Bayesian Inference

arXiv: https://arxiv.org/abs/2003.02629 · HTML: https://mlsanity.com/paper/2003.02629/

## Key facts

- Cited by 6 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 28 Feb 2020.

## Built on by (most cited first, 6 of 6)

- [MC-CIM: Compute-in-Memory with Monte-Carlo Dropouts for Bayesian Edge Intelligence](https://mlsanity.com/paper/2111.07125/) (2021)
- [Intelligent Sensing-to-Action for Robust Autonomy at the Edge: Opportunities and Challenges](https://mlsanity.com/paper/2502.02692/) (2025)
- [Bayesian Inference on Binary Spiking Networks Leveraging Nanoscale Device Stochasticity](https://mlsanity.com/paper/2302.01302/) (2023)
- [Memory-Immersed Collaborative Digitization for Area-Efficient Compute-in-Memory Deep Learning](https://mlsanity.com/paper/2307.03863/) (2023)
- [ENOS: Energy-Aware Network Operator Search for Hybrid Digital and Compute-in-Memory DNN Accelerators](https://mlsanity.com/paper/2104.05217/) (2021)
- [Towards Model-Size Agnostic, Compute-Free, Memorization-based Inference of Deep Learning](https://mlsanity.com/paper/2307.07631/) (2023)

## Abstract (arXiv)

This work discusses the implementation of Markov Chain Monte Carlo (MCMC) sampling from an arbitrary Gaussian mixture model (GMM) within SRAM. We show a novel architecture of SRAM by embedding it with random number generators (RNGs), digital-to-analog converters (DACs), and analog-to-digital converters (ADCs) so that SRAM arrays can be used for high performance Metropolis-Hastings (MH) algorithm-based MCMC sampling. Most of the expensive computations are performed within the SRAM and can be parallelized for high speed sampling. Our iterative compute flow minimizes data movement during sampling. We characterize power-performance trade-off of our design by simulating on 45 nm CMOS technology. For a two-dimensional, two mixture GMM, the implementation consumes ~ 91 micro-Watts power per sampling iteration and produces 500 samples in 2000 clock cycles on an average at 1 GHz clock frequency. Our study highlights interesting insights on how low-level hardware non-idealities can affect high-level sampling characteristics, and recommends ways to optimally operate SRAM within area/power constraints for high performance sampling.