# Hardware Security for and beyond CMOS Technology

arXiv: https://arxiv.org/abs/2001.08780 · HTML: https://mlsanity.com/paper/2001.08780/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 23 Jan 2020.

## Built on by (most cited first, 4 of 4)

- [LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust](https://mlsanity.com/paper/2405.07061/) (2024)
- [RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation](https://mlsanity.com/paper/2411.17569/) (2024)
- [Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs](https://mlsanity.com/paper/2211.16495/) (2022)
- [TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans](https://mlsanity.com/paper/2405.05590/) (2024)

## Abstract (arXiv)

As with most aspects of electronic systems and integrated circuits, hardware security has traditionally evolved around the dominant CMOS technology. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also to advance the notion of hardware security. In this paper, I first provide an overview on hardware security in general. Next, I review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and related transistors, (iv) nanowires and related transistors, and (v) 3D and 2.5D integration. I then discuss their application to advance hardware security and also outline related challenges.