# A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design

arXiv: https://arxiv.org/abs/2001.05348 · HTML: https://mlsanity.com/paper/2001.05348/

## Key facts

- Cited by 5 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 8 Jan 2020.

## Built on by (most cited first, 5 of 5)

- [Timing-Based Backpropagation in Spiking Neural Networks Without Single-Spike Restrictions](https://mlsanity.com/paper/2211.16113/) (2022)
- [Sparse-firing regularization methods for spiking neural networks with time-to-first spike coding](https://mlsanity.com/paper/2307.13007/) (2023)
- [Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks](https://mlsanity.com/paper/2106.10382/) (2021)
- [Spiking neural networks trained via proxy](https://mlsanity.com/paper/2109.13208/) (2021)
- [Scalable Training of Continuous-Time Spiking Neural Networks with Differentiable Spike-Time Discretization](https://mlsanity.com/paper/2607.14672/) (2026)

## Abstract (arXiv)

Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in the form of spikes. SNNs are expected to provide not only new machine-learning algorithms, but also energy-efficient computational models when implemented in VLSI circuits. In this paper, we propose a novel supervised learning algorithm for SNNs based on temporal coding. A spiking neuron in this algorithm is designed to facilitate analog VLSI implementations with analog resistive memory, by which ultra-high energy efficiency can be achieved. We also propose several techniques to improve the performance on a recognition task, and show that the classification accuracy of the proposed algorithm is as high as that of the state-of-the-art temporal coding SNN algorithms on the MNIST dataset. Finally, we discuss the robustness of the proposed SNNs against variations that arise from the device manufacturing process and are unavoidable in analog VLSI implementation. We also propose a technique to suppress the effects of variations in the manufacturing process on the recognition performance.