# PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM

arXiv: https://arxiv.org/abs/1912.11516 · HTML: https://mlsanity.com/paper/1912.11516/

## Key facts

- Cited by 17 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 24 Dec 2019.

## Built on by (most cited first, 17 of 17)

- [X-Former: In-Memory Acceleration of Transformers](https://mlsanity.com/paper/2303.07470/) (2023)
- [Towards Efficient In-memory Computing Hardware for Quantized Neural Networks: State-of-the-art, Open Challenges and Perspectives](https://mlsanity.com/paper/2307.03936/) (2023)
- [LLS: Local Learning Rule for Deep Neural Networks Inspired by Neural Activity Synchronization](https://mlsanity.com/paper/2405.15868/) (2024)
- [LANCE: Low Rank Activation Compression for Efficient On-Device Continual Learning](https://mlsanity.com/paper/2509.21617/) (2025)
- [An Experimental Evaluation of Machine Learning Training on a Real Processing-in-Memory System](https://mlsanity.com/paper/2207.07886/) (2022)
- [FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators](https://mlsanity.com/paper/2401.10522/) (2024)
- [Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures](https://mlsanity.com/paper/2501.09588/) (2025)
- [Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutions](https://mlsanity.com/paper/2212.13707/) (2022)
- [TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systems](https://mlsanity.com/paper/2304.01951/) (2023)
- [Comprehensive Benchmarking of Binary Neural Networks on NVM Crossbar Architectures](https://mlsanity.com/paper/2308.06227/) (2023)
- [Current Opinions on Memristor-Accelerated Machine Learning Hardware](https://mlsanity.com/paper/2501.12644/) (2025)
- [Making Analog Training Scale: Co-Designing Mapping, Optimizer, and Converters](https://mlsanity.com/paper/2609.36584/) (2026)
- [NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators](https://mlsanity.com/paper/2211.05730/) (2022)
- [Pruning for Improved ADC Efficiency in Crossbar-based Analog In-memory Accelerators](https://mlsanity.com/paper/2403.13082/) (2024)
- [A Collaborative PIM Computing Optimization Framework for Multi-Tenant DNN](https://mlsanity.com/paper/2408.04812/) (2024)
- [M2RU: Memristive Minion Recurrent Unit for On-Chip Continual Learning at the Edge](https://mlsanity.com/paper/2512.17299/) (2025)
- [ThRIve: Thermally Robust CNN Inference via Low-Rank Adaptation in Heterogeneous PIM Architectures](https://mlsanity.com/paper/2607.17091/) (2026)

## Abstract (arXiv)

The wide adoption of deep neural networks has been accompanied by ever-increasing energy and performance demands due to the expensive nature of training them. Numerous special-purpose architectures have been proposed to accelerate training: both digital and hybrid digital-analog using resistive RAM (ReRAM) crossbars. ReRAM-based accelerators have demonstrated the effectiveness of ReRAM crossbars at performing matrix-vector multiplication operations that are prevalent in training. However, they still suffer from inefficiency due to the use of serial reads and writes for performing the weight gradient and update step. A few works have demonstrated the possibility of performing outer products in crossbars, which can be used to realize the weight gradient and update step without the use of serial reads and writes. However, these works have been limited to low precision operations which are not sufficient for typical training workloads. Moreover, they have been confined to a limited set of training algorithms for fully-connected layers only. To address these limitations, we propose a bit-slicing technique for enhancing the precision of ReRAM-based outer products, which is substantially different from bit-slicing for matrix-vector multiplication only. We incorporate this technique into a crossbar architecture with three variants catered to different training algorithms. To evaluate our design on different types of layers in neural networks (fully-connected, convolutional, etc.) and training algorithms, we develop PANTHER, an ISA-programmable training accelerator with compiler support. Our evaluation shows that PANTHER achieves up to 8.02×, 54.21×, and 103× energy reductions as well as 7.16×, 4.02×, and 16× execution time reductions compared to digital accelerators, ReRAM-based accelerators, and GPUs, respectively.