# Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network

arXiv: https://arxiv.org/abs/1912.00402 · HTML: https://mlsanity.com/paper/1912.00402/

## Key facts

- Cited by 8 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 1 Dec 2019.

## Built on by (most cited first, 8 of 8)

- [An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble](https://mlsanity.com/paper/2106.15412/) (2021)
- [Preference-Aware Constrained Multi-Objective Bayesian Optimization](https://mlsanity.com/paper/2303.13034/) (2023)
- [Automated Circuit Sizing with Multi-objective Optimization based on Differential Evolution and Bayesian Inference](https://mlsanity.com/paper/2206.02391/) (2022)
- [CktGen: Automated Analog Circuit Design with Generative Artificial Intelligence](https://mlsanity.com/paper/2410.00995/) (2024)
- [BoA-PTA, A Bayesian Optimization Accelerated Error-Free SPICE Solver](https://mlsanity.com/paper/2108.00257/) (2021)
- [LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces](https://mlsanity.com/paper/2109.00617/) (2021)
- [Finding the Needle in a Haystack: Test-Time Analog Circuit Representation Adaptation for Bayesian Optimization](https://mlsanity.com/paper/2608.12687/) (2026)
- [AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing](https://mlsanity.com/paper/2609.25873/) (2026)

## Abstract (arXiv)

Bayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. The computational complexity of training is O(N 3 ), and the computation complexity of prediction is O(N 2 ), where N is the number of training data. Gaussian process model can also be derived from a weight space view, where the original data are mapped to feature space, and the kernel function is defined as the inner product of nonlinear features. In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. We use deep neural network to extract good feature representations, and then define Gaussian process using the extracted features. Model averaging method is applied to improve the quality of uncertainty prediction. Compared to Gaussian process model with explicitly defined kernel functions, the neural-network-based Gaussian process model can automatically learn a kernel function from data, which makes it possible to provide more accurate predictions and thus accelerate the follow-up optimization procedure. Also, the neural-network-based model has O(N) training time and constant prediction time. The efficiency of the proposed method has been verified by two real-world analog circuits.