# DRiLLS: Deep Reinforcement Learning for Logic Synthesis

arXiv: https://arxiv.org/abs/1911.04021 · HTML: https://mlsanity.com/paper/1911.04021/

## Key facts

- Cited by 47 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 11 Nov 2019.

## Built on by (most cited first, 30 of 47)

- [Machine Learning for Electronic Design Automation: A Survey](https://mlsanity.com/paper/2102.03357/) (2021)
- [A Survey of Machine Learning for Computer Architecture and Systems](https://mlsanity.com/paper/2102.07952/) (2021)
- [LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation](https://mlsanity.com/paper/2401.12224/) (2023)
- [OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis](https://mlsanity.com/paper/2110.11292/) (2021)
- [BOiLS: Bayesian Optimisation for Logic Synthesis](https://mlsanity.com/paper/2111.06178/) (2021)
- [Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis](https://mlsanity.com/paper/2312.01022/) (2023)
- [Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Design](https://mlsanity.com/paper/2203.15913/) (2022)
- [DevFormer: A Symmetric Transformer for Context-Aware Device Placement](https://mlsanity.com/paper/2205.13225/) (2022)
- [DeepTPI: Test Point Insertion with Deep Reinforcement Learning](https://mlsanity.com/paper/2206.06975/) (2022)
- [Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization](https://mlsanity.com/paper/2401.12205/) (2024)
- [Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs](https://mlsanity.com/paper/2405.06758/) (2024)
- [LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models](https://mlsanity.com/paper/2201.08455/) (2022)
- [A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design](https://mlsanity.com/paper/2309.03208/) (2023)
- [Circuit Transformer: A Transformer That Preserves Logical Equivalence](https://mlsanity.com/paper/2403.13838/) (2024)
- [LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models](https://mlsanity.com/paper/2510.15899/) (2025)
- [AISYN: AI-driven Reinforcement Learning-Based Logic Synthesis Framework](https://mlsanity.com/paper/2302.06415/) (2023)
- [Logic Synthesis with Generative Deep Neural Networks](https://mlsanity.com/paper/2406.04699/) (2024)
- [MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning](https://mlsanity.com/paper/2407.18110/) (2024)
- [Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges](https://mlsanity.com/paper/2208.13885/) (2022)
- [INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search](https://mlsanity.com/paper/2305.13164/) (2023)
- [OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis](https://mlsanity.com/paper/2411.09422/) (2024)
- [VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code](https://mlsanity.com/paper/2506.07239/) (2025)
- [Rethinking Reinforcement Learning based Logic Synthesis](https://mlsanity.com/paper/2205.07614/) (2022)
- [Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning](https://mlsanity.com/paper/2312.14536/) (2023)
- [BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation](https://mlsanity.com/paper/2401.10753/) (2024)
- [ShortCircuit: AlphaZero-Driven Circuit Design](https://mlsanity.com/paper/2408.09858/) (2024)
- [MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization](https://mlsanity.com/paper/2409.06077/) (2024)
- [Too Big to Fail? Active Few-Shot Learning Guided Logic Synthesis](https://mlsanity.com/paper/2204.02368/) (2022)
- [HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector Generation](https://mlsanity.com/paper/2207.11312/) (2022)
- [The prediction of the quality of results in Logic Synthesis using Transformer and Graph Neural Networks](https://mlsanity.com/paper/2207.11437/) (2022)

## Abstract (arXiv)

Logic synthesis requires extensive tuning of the synthesis optimization flow where the quality of results (QoR) depends on the sequence of optimizations used. Efficient design space exploration is challenging due to the exponential number of possible optimization permutations. Therefore, automating the optimization process is necessary. In this work, we propose a novel reinforcement learning-based methodology that navigates the optimization space without human intervention. We demonstrate the training of an Advantage Actor Critic (A2C) agent that seeks to minimize area subject to a timing constraint. Using the proposed methodology, designs can be optimized autonomously with no-humans in-loop. Evaluation on the comprehensive EPFL benchmark suite shows that the agent outperforms existing exploration methodologies and improves QoRs by an average of 13%.