# High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS

arXiv: https://arxiv.org/abs/1909.07514 · HTML: https://mlsanity.com/paper/1909.07514/

## Key facts

- Cited by 10 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 16 Sep 2019.

## Built on by (most cited first, 10 of 10)

- [An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices](https://mlsanity.com/paper/2105.13904/) (2021)
- [Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures](https://mlsanity.com/paper/2201.12480/) (2022)
- [Towards Efficient In-memory Computing Hardware for Quantized Neural Networks: State-of-the-art, Open Challenges and Perspectives](https://mlsanity.com/paper/2307.03936/) (2023)
- [Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units](https://mlsanity.com/paper/2304.09258/) (2023)
- [StoX-Net: Stochastic Processing of Partial Sums for Efficient In-Memory Computing DNN Accelerators](https://mlsanity.com/paper/2407.12378/) (2024)
- [Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune](https://mlsanity.com/paper/2104.06377/) (2021)
- [Current Opinions on Memristor-Accelerated Machine Learning Hardware](https://mlsanity.com/paper/2501.12644/) (2025)
- [Approximate ADCs for In-Memory Computing](https://mlsanity.com/paper/2408.06390/) (2024)
- [CNN-Based Automated Parameter Extraction Framework for Modeling Memristive Devices](https://mlsanity.com/paper/2511.07926/) (2025)
- [IMC-CLINIC: Coupled Loss-Informed Newton Iterations for Clipping in Analog In-Memory Computing](https://mlsanity.com/paper/2609.35586/) (2026)

## Abstract (arXiv)

Deep learning hardware designs have been bottlenecked by conventional memories such as SRAM due to density, leakage and parallel computing challenges. Resistive devices can address the density and volatility issues, but have been limited by peripheral circuit integration. In this work, we demonstrate a scalable RRAM based in-memory computing design, termed XNOR-RRAM, which is fabricated in a 90nm CMOS technology with monolithic integration of RRAM devices between metal 1 and 2. We integrated a 128x64 RRAM array with CMOS peripheral circuits including row/column decoders and flash analog-to-digital converters (ADCs), which collectively become a core component for scalable RRAM-based in-memory computing towards large deep neural networks (DNNs). To maximize the parallelism of in-memory computing, we assert all 128 wordlines of the RRAM array simultaneously, perform analog computing along the bitlines, and digitize the bitline voltages using ADCs. The resistance distribution of low resistance states is tightened by write-verify scheme, and the ADC offset is calibrated. Prototype chip measurements show that the proposed design achieves high binary DNN accuracy of 98.5% for MNIST and 83.5% for CIFAR-10 datasets, respectively, with energy efficiency of 24 TOPS/W and 158 GOPS throughput. This represents 5.6X, 3.2X, 14.1X improvements in throughput, energy-delay product (EDP), and energy-delay-squared product (ED2P), respectively, compared to the state-of-the-art literature. The proposed XNOR-RRAM can enable intelligent functionalities for area-/energy-constrained edge computing devices.