# Automatic Compiler Based FPGA Accelerator for CNN Training

arXiv: https://arxiv.org/abs/1908.06724 · HTML: https://mlsanity.com/paper/1908.06724/

## Key facts

- Cited by 7 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 15 Aug 2019.

## Built on by (most cited first, 7 of 7)

- [EF-Train: Enable Efficient On-device CNN Training on FPGA Through Data Reshaping for Online Adaptation or Personalization](https://mlsanity.com/paper/2202.10935/) (2022)
- [Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge](https://mlsanity.com/paper/2210.10922/) (2022)
- [Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design](https://mlsanity.com/paper/2309.13015/) (2023)
- [Ultra Memory-Efficient On-FPGA Training of Transformers via Tensor-Compressed Optimization](https://mlsanity.com/paper/2501.06663/) (2025)
- [Ultrafast On-Chip Online Learning via Spline Locality in Kolmogorov-Arnold Networks](https://mlsanity.com/paper/2602.02056/) (2026)
- [Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review](https://mlsanity.com/paper/2603.08740/) (2026)
- [LocalTrain: Integer-Only Local Learning for Energy-Efficient CNN Training on Edge FPGAs](https://mlsanity.com/paper/2610.17099/) (2026)

## Abstract (arXiv)

Training of convolutional neural networks (CNNs)on embedded platforms to support on-device learning is earning vital importance in recent days. Designing flexible training hard-ware is much more challenging than inference hardware, due to design complexity and large computation/memory requirement. In this work, we present an automatic compiler-based FPGA accelerator with 16-bit fixed-point precision for complete CNNtraining, including Forward Pass (FP), Backward Pass (BP) and Weight Update (WU). We implemented an optimized RTL library to perform training-specific tasks and developed an RTL compiler to automatically generate FPGA-synthesizable RTL based on user-defined constraints. We present a new cyclic weight storage/access scheme for on-chip BRAM and off-chip DRAMto efficiently implement non-transpose and transpose operations during FP and BP phases, respectively. Representative CNNs for CIFAR-10 dataset are implemented and trained on Intel Stratix 10-GX FPGA using proposed hardware architecture, demonstrating up to 479 GOPS performance.