# Near-Memory Computing: Past, Present, and Future

arXiv: https://arxiv.org/abs/1908.02640 · HTML: https://mlsanity.com/paper/1908.02640/

## Key facts

- Cited by 5 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 7 Aug 2019.

## Built on by (most cited first, 5 of 5)

- [Chameleon: a Heterogeneous and Disaggregated Accelerator System for Retrieval-Augmented Language Models](https://mlsanity.com/paper/2310.09949/) (2023)
- [FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks](https://mlsanity.com/paper/2201.07634/) (2022)
- [DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference](https://mlsanity.com/paper/2305.07376/) (2023)
- [AI Compute Architecture and Evolution Trends](https://mlsanity.com/paper/2508.21394/) (2025)
- [CiMNet: Towards Joint Optimization for DNN Architecture and Configuration for Compute-In-Memory Hardware](https://mlsanity.com/paper/2402.11780/) (2024)

## Abstract (arXiv)

The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integration technologies has made the decade-old concept of coupling compute units close to the memory --- called near-memory computing (NMC) --- more viable. Processing right at the "home" of data can significantly diminish the data movement problem of data-intensive applications. In this paper, we survey the prior art on NMC across various dimensions (architecture, applications, tools, etc.) and identify the key challenges and open issues with future research directions. We also provide a glimpse of our approach to near-memory computing that includes i) NMC specific microarchitecture independent application characterization ii) a compiler framework to offload the NMC kernels on our target NMC platform and iii) an analytical model to evaluate the potential of NMC.