# BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks

arXiv: https://arxiv.org/abs/1907.10515 · HTML: https://mlsanity.com/paper/1907.10515/

## Key facts

- Cited by 11 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 23 Jul 2019.

## Built on by (most cited first, 11 of 11)

- [Machine Learning for Electronic Design Automation: A Survey](https://mlsanity.com/paper/2102.03357/) (2021)
- [A Survey of Machine Learning for Computer Architecture and Systems](https://mlsanity.com/paper/2102.07952/) (2021)
- [Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Design](https://mlsanity.com/paper/2203.15913/) (2022)
- [AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design](https://mlsanity.com/paper/2407.18272/) (2024)
- [Supervised Learning for Analog and RF Circuit Design: Benchmarks and Comparative Insights](https://mlsanity.com/paper/2501.11839/) (2025)
- [A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation](https://mlsanity.com/paper/2204.09579/) (2022)
- [Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks](https://mlsanity.com/paper/2311.17073/) (2023)
- [Emerging ML-AI Techniques for Analog and RF EDA](https://mlsanity.com/paper/2506.00007/) (2025)
- [The Dark Side: Security Concerns in Machine Learning for EDA](https://mlsanity.com/paper/2203.10597/) (2022)
- [Intelligent Circuit Design and Implementation with Machine Learning](https://mlsanity.com/paper/2206.03032/) (2022)
- [Lighthouse RL: Sample-Efficient Circuit Optimization via Strategic Reset Points](https://mlsanity.com/paper/2607.14008/) (2026)

## Abstract (arXiv)

The discrepancy between post-layout and schematic simulation results continues to widen in analog design due in part to the domination of layout parasitics. This paradigm shift is forcing designers to adopt design methodologies that seamlessly integrate layout effects into the standard design flow. Hence, any simulation-based optimization framework should take into account time-consuming post-layout simulation results. This work presents a learning framework that learns to reduce the number of simulations of evolutionary-based combinatorial optimizers, using a DNN that discriminates against generated samples, before running simulations. Using this approach, the discriminator achieves at least two orders of magnitude improvement on sample efficiency for several large circuit examples including an optical link receiver layout.