# eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform

arXiv: https://arxiv.org/abs/1906.05096 · HTML: https://mlsanity.com/paper/1906.05096/

## Key facts

- Cited by 8 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 3 Jun 2019.

## Built on by (most cited first, 8 of 8)

- [EfficientNav: Towards On-Device Object-Goal Navigation with Navigation Map Caching and Retrieval](https://mlsanity.com/paper/2510.18546/) (2025)
- [Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform](https://mlsanity.com/paper/2203.15439/) (2022)
- [An Energy-Efficient Quad-Camera Visual System for Autonomous Machines on FPGA Platform](https://mlsanity.com/paper/2104.00192/) (2021)
- [Faster than Fast: Accelerating Oriented FAST Feature Detection on Low-end Embedded GPUs](https://mlsanity.com/paper/2506.07164/) (2025)
- [A Motion-Aware Vector Quantization Framework with Centroid Reuse for Efficient VLA Inference](https://mlsanity.com/paper/2607.24148/) (2026)
- [HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices](https://mlsanity.com/paper/2408.12840/) (2024)
- [Accelerated Feature Detectors for Visual SLAM: A Comparative Study of FPGA vs GPU](https://mlsanity.com/paper/2510.13546/) (2025)
- [HexVIO: Towards All-Day Stereo-Inertial Tracking Through Commodity DSPs](https://mlsanity.com/paper/2610.03283/) (2026)

## Abstract (arXiv)

Simultaneous Localization and Mapping (SLAM) is a critical task for autonomous navigation. However, due to the computational complexity of SLAM algorithms, it is very difficult to achieve real-time implementation on low-power platforms.We propose an energy efficient architecture for real-time ORB (Oriented-FAST and Rotated- BRIEF) based visual SLAM system by accelerating the most time consuming stages of feature extraction and matching on FPGA platform.Moreover, the original ORB descriptor pattern is reformed as a rotational symmetric manner which is much more hardware friendly. Optimizations including rescheduling and parallelizing are further utilized to improve the throughput and reduce the memory footprint. Compared with Intel i7 and ARM Cortex-A9 CPUs on TUM dataset, our FPGA realization achieves up to 3X and 31X frame rate improvement, as well as up to 71X and 25X energy efficiency improvement, respectively.