# Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

arXiv: https://arxiv.org/abs/1905.03852 · HTML: https://mlsanity.com/paper/1905.03852/

## Key facts

- Cited by 8 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 6 May 2019.

## Built on by (most cited first, 8 of 8)

- [Machine Learning for Electronic Design Automation: A Survey](https://mlsanity.com/paper/2102.03357/) (2021)
- [A Survey of Machine Learning for Computer Architecture and Systems](https://mlsanity.com/paper/2102.07952/) (2021)
- [IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning](https://mlsanity.com/paper/2102.08138/) (2021)
- [Pushing the Limits of Machine Design: Automated CPU Design with AI](https://mlsanity.com/paper/2306.12456/) (2023)
- [LEAPER: Fast and Accurate FPGA-based System Performance Prediction via Transfer Learning](https://mlsanity.com/paper/2208.10606/) (2022)
- [A Benchmark on Directed Graph Representation Learning in Hardware Designs](https://mlsanity.com/paper/2410.06460/) (2024)
- [CapBench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extraction](https://mlsanity.com/paper/2604.11202/) (2026)
- [QiMeng: Fully Automated Hardware and Software Design for Processor Chip](https://mlsanity.com/paper/2506.05007/) (2025)

## Abstract (arXiv)

High-level synthesis (HLS) shortens the development time of hardware designs and enables faster design space exploration at a higher abstraction level. Optimization of complex applications in HLS is challenging due to the effects of implementation issues such as routing congestion. Routing congestion estimation is absent or inaccurate in existing HLS design methods and tools. Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation. However, routability, a serious concern in FPGA designs, has been difficult to evaluate in HLS without analyzing post-implementation details after Place and Route. To this end, we propose a novel method to predict routing congestion in HLS using machine learning and map the expected congested regions in the design to the relevant high-level source code. This is greatly beneficial in early identification of routability oriented bottlenecks in the high-level source code without running time-consuming register-transfer level (RTL) implementation flow. Experiments demonstrate that our approach accurately estimates vertical and horizontal routing congestion with errors of 6.71% and 10.05% respectively. By presenting Face Detection application as a case study, we show that by discovering the bottlenecks in high-level source code, routing congestion can be easily and quickly resolved compared to the efforts involved in RTL implementation and design feedback.