# Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets

arXiv: https://arxiv.org/abs/1904.07077 · HTML: https://mlsanity.com/paper/1904.07077/

## Key facts

- Cited by 8 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 15 Apr 2019.

## Built on by (most cited first, 8 of 8)

- [RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUs](https://mlsanity.com/paper/2304.04716/) (2023)
- [Accelerating Exact Combinatorial Optimization via RL-based Initialization -- A Case Study in Scheduling](https://mlsanity.com/paper/2308.11652/) (2023)
- [MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning](https://mlsanity.com/paper/2407.18110/) (2024)
- [Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data](https://mlsanity.com/paper/2203.16009/) (2022)
- [Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent](https://mlsanity.com/paper/2402.06034/) (2024)
- [Variational Label-Correlation Enhancement for Congestion Prediction](https://mlsanity.com/paper/2308.00529/) (2023)
- [Improving Routability Prediction via NAS Using a Smooth One-shot Augmented Predictor](https://mlsanity.com/paper/2411.14296/) (2024)
- [VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification](https://mlsanity.com/paper/2603.11075/) (2026)

## Abstract (arXiv)

Physical design process commonly consumes hours to days for large designs, and routing is known as the most critical step. Demands for accurate routing quality prediction raise to a new level to accelerate hardware innovation with advanced technology nodes. This work presents an approach that forecasts the density of all routing channels over the entire floorplan, with features collected up to placement, using conditional GANs. Specifically, forecasting the routing congestion is constructed as an image translation (colorization) problem. The proposed approach is applied to a) placement exploration for minimum congestion, b) constrained placement exploration and c) forecasting congestion in real-time during incremental placement, using eight designs targeting a fixed FPGA architecture.