# Cause Mining and Controller Synthesis with STL

arXiv: https://arxiv.org/abs/1904.03649 · HTML: https://mlsanity.com/paper/1904.03649/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 7 Apr 2019.

## Built on by (most cited first, 2 of 2)

- [Retrieval-Augmented Mining of Temporal Logic Specifications from Data](https://mlsanity.com/paper/2405.14355/) (2024)
- [Bridging Logic and Learning: Decoding Temporal Logic Embeddings via Transformers](https://mlsanity.com/paper/2507.07808/) (2025)

## Abstract (arXiv)

Formal control of cyber-physical systems allows for synthesis of control strategies from rich specifications such as temporal logics. However, the classes of systems that the formal approaches can be applied to is limited due to the computational complexity. Furthermore, the synthesis problem becomes even harder when non-determinism or stochasticity is considered. In this work, we propose an alternative approach. First, we mark the unwanted events on the traces of the system and generate a controllable cause representing these events as a Signal Temporal Logic (STL) formula. Then, we synthesize a controller based on this formula to avoid the satisfaction of it. Our approach is applicable to any system with finitely many control choices. While we can not guarantee correctness, i.e., the unwanted events will never occur, we show on an example that the proposed approach reduces the number of the unwanted events. In particular, we validate it for the congestion avoidance problem in a traffic network.