# LUTNet: Rethinking Inference in FPGA Soft Logic

arXiv: https://arxiv.org/abs/1904.00938 · HTML: https://mlsanity.com/paper/1904.00938/

## Key facts

- Cited by 28 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 1 Apr 2019.

## Built on by (most cited first, 28 of 28)

- [Convolutional Differentiable Logic Gate Networks](https://mlsanity.com/paper/2411.04732/) (2024)
- [PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference](https://mlsanity.com/paper/2309.02334/) (2023)
- [NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions](https://mlsanity.com/paper/2403.00849/) (2024)
- [NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference](https://mlsanity.com/paper/2504.00592/) (2025)
- [PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs](https://mlsanity.com/paper/2406.04910/) (2024)
- [Enabling Binary Neural Network Training on the Edge](https://mlsanity.com/paper/2102.04270/) (2021)
- [Reverse Derivative Ascent: A Categorical Approach to Learning Boolean Circuits](https://mlsanity.com/paper/2101.10488/) (2021)
- [PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruning](https://mlsanity.com/paper/2501.08043/) (2025)
- [FPGA Resource-aware Structured Pruning for Real-Time Neural Networks](https://mlsanity.com/paper/2308.05170/) (2023)
- [LILogic Net: Compact Logic Gate Networks with Learnable Connectivity for Efficient Hardware Deployment](https://mlsanity.com/paper/2511.12340/) (2025)
- [A Method for Optimizing Connections in Differentiable Logic Gate Networks](https://mlsanity.com/paper/2507.06173/) (2025)
- [NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic](https://mlsanity.com/paper/2104.05421/) (2021)
- [A Scalable, Interpretable, Verifiable & Differentiable Logic Gate Convolutional Neural Network Architecture From Truth Tables](https://mlsanity.com/paper/2208.08609/) (2022)
- [Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference](https://mlsanity.com/paper/2112.02346/) (2021)
- [LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference](https://mlsanity.com/paper/2411.11852/) (2024)
- [FPGA-Enabled Machine Learning Applications in Earth Observation: A Systematic Review](https://mlsanity.com/paper/2506.03938/) (2025)
- [TeLLMe v2: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs](https://mlsanity.com/paper/2510.15926/) (2025)
- [A Lightweight Multi-Attack CAN Intrusion Detection System on Hybrid FPGAs](https://mlsanity.com/paper/2401.10689/) (2024)
- [Runtime Tunable Tsetlin Machines for Edge Inference on eFPGAs](https://mlsanity.com/paper/2502.07823/) (2025)
- [Optimizing Neural Networks with Learnable Non-Linear Activation Functions via Lookup-Based FPGA Acceleration](https://mlsanity.com/paper/2508.17069/) (2025)
- [Inter-patient ECG Arrhythmia Classification with LGNs and LUTNs](https://mlsanity.com/paper/2601.11433/) (2026)
- [Continuous-Flow Data-Rate-Aware CNN Inference on FPGA](https://mlsanity.com/paper/2601.19940/) (2026)
- [Learning Compact Boolean Networks](https://mlsanity.com/paper/2602.05830/) (2026)
- [A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN](https://mlsanity.com/paper/2401.12234/) (2024)
- [Quantization Effects of Artificial Neural Networks for Embedded Edge-Computing Applications](https://mlsanity.com/paper/2511.05479/) (2025)
- [Data-Rate-Aware High-Speed CNN Inference on FPGAs](https://mlsanity.com/paper/2603.08726/) (2026)
- [Bern2Edge: A Neurosymbolic Compiler for Edge Deployment via Bernstein Polynomial Networks](https://mlsanity.com/paper/2608.20497/) (2026)
- [Logic Gate Networks and Lookup Table Networks as Lightweight Hardware Classifiers for Inter-patient ECG Arrhythmia Classification](https://mlsanity.com/paper/2609.32854/) (2026)

## Abstract (arXiv)

Research has shown that deep neural networks contain significant redundancy, and that high classification accuracies can be achieved even when weights and activations are quantised down to binary values. Network binarisation on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarised neural network implementation, we achieve twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable.