# MRAM Co-designed Processing-in-Memory CNN Accelerator for Mobile and IoT Applications

arXiv: https://arxiv.org/abs/1811.12179 · HTML: https://mlsanity.com/paper/1811.12179/

## Key facts

- Cited by 5 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 26 Nov 2018.

## Built on by (most cited first, 5 of 5)

- [An improved LogNNet classifier for IoT application](https://mlsanity.com/paper/2105.14412/) (2021)
- [GnetSeg: Semantic Segmentation Model Optimized on a 224mW CNN Accelerator Chip at the Speed of 318FPS](https://mlsanity.com/paper/2101.10444/) (2021)
- [GnetDet: Object Detection Optimized on a 224mW CNN Accelerator Chip at the Speed of 106FPS](https://mlsanity.com/paper/2103.15756/) (2021)
- [Evaluation of STT-MRAM as a Scratchpad for Training in ML Accelerators](https://mlsanity.com/paper/2308.02024/) (2023)
- [FLARE: FP-Less PTQ and Low-ENOB ADC Based AMS-PiM for Error-Resilient, Fast, and Efficient Transformer Acceleration](https://mlsanity.com/paper/2411.14733/) (2024)

## Abstract (arXiv)

We designed a device for Convolution Neural Network applications with non-volatile MRAM memory and computing-in-memory co-designed architecture. It has been successfully fabricated using 22nm technology node CMOS Si process. More than 40MB MRAM density with 9.9TOPS/W are provided. It enables multiple models within one single chip for mobile and IoT device applications.