# Sparse Winograd Convolutional neural networks on small-scale systolic arrays

arXiv: https://arxiv.org/abs/1810.01973 · HTML: https://mlsanity.com/paper/1810.01973/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 3 Oct 2018.

## Built on by (most cited first, 4 of 4)

- [WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs](https://mlsanity.com/paper/2107.04244/) (2021)
- [EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators](https://mlsanity.com/paper/2202.02310/) (2022)
- [Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator](https://mlsanity.com/paper/2408.07404/) (2024)
- [Fast Convolution based on Winograd Minimum Filtering: Introduction and Development](https://mlsanity.com/paper/2111.00977/) (2021)

## Abstract (arXiv)

The reconfigurability, energy-efficiency, and massive parallelism on FPGAs make them one of the best choices for implementing efficient deep learning accelerators. However, state-of-art implementations seldom consider the balance between high throughput of computation power and the ability of the memory subsystem to support it. In this paper, we implement an accelerator on FPGA by combining the sparse Winograd convolution, clusters of small-scale systolic arrays, and a tailored memory layout design. We also provide an analytical model analysis for the general Winograd convolution algorithm as a design reference. Experimental results on VGG16 show that it achieves very high computational resource utilization, 20x ~ 30x energy efficiency, and more than 5x speedup compared with the dense implementation.