# A CNN Accelerator on FPGA Using Depthwise Separable Convolution

arXiv: https://arxiv.org/abs/1809.01536 · HTML: https://mlsanity.com/paper/1809.01536/

## Key facts

- Cited by 8 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 3 Sep 2018.

## Built on by (most cited first, 8 of 8)

- [A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs](https://mlsanity.com/paper/2107.12824/) (2021)
- [BLPnet: A new DNN model and Bengali OCR engine for Automatic License Plate Recognition](https://mlsanity.com/paper/2202.12250/) (2022)
- [FastStamp: Accelerating Neural Steganography and Digital Watermarking of Images on FPGAs](https://mlsanity.com/paper/2209.12391/) (2022)
- [Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays](https://mlsanity.com/paper/2204.09515/) (2022)
- [RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI](https://mlsanity.com/paper/2511.21232/) (2025)
- [Phantom: A High-Performance Computational Core for Sparse Convolutional Neural Networks](https://mlsanity.com/paper/2111.05002/) (2021)
- [NeuralMatrix: Compute the Entire Neural Networks with Linear Matrix Operations for Efficient Inference](https://mlsanity.com/paper/2305.14405/) (2023)
- [Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems](https://mlsanity.com/paper/2608.28160/) (2026)

## Abstract (arXiv)

Convolutional neural networks (CNNs) have been widely deployed in the fields of computer vision and pattern recognition because of their high accuracy. However, large convolution operations are computing-intensive that often requires a powerful computing platform such as Graphics Processing Unit (GPU). This makes it difficult to apply CNNs to portable devices. The state-of-the-art CNNs, such as MobileNetV2 and Xception, adopt depthwise separable convolution to replace the standard convolution for embedded platforms. That significantly reduces operations and parameters with only limited loss in accuracy. This highly structured model is very suitable for Field-Programmable Gate Array (FPGA) implementation. In this paper, a scalable high performance depthwise separable convolution optimized CNN accelerator is proposed. The accelerator can be fit into an FPGA of different sizes, provided the balancing between hardware resources and processing speed. As an example, MobileNetV2 is implemented on Arria 10 SoC FPGA, and the results show this accelerator can classify each picture from ImageNet in 3.75ms, which is about 266.6 frames per second. This achieves 20x speedup if compared to CPU.