# Anatomy Of High-Performance Deep Learning Convolutions On SIMD Architectures

arXiv: https://arxiv.org/abs/1808.05567 · HTML: https://mlsanity.com/paper/1808.05567/

## Key facts

- Cited by 12 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 16 Aug 2018.

## Built on by (most cited first, 12 of 12)

- [Tensor Processing Primitives: A Programming Abstraction for Efficiency and Portability in Deep Learning & HPC Workloads](https://mlsanity.com/paper/2104.05755/) (2021)
- [LookupFFN: Making Transformers Compute-lite for CPU inference](https://mlsanity.com/paper/2403.07221/) (2024)
- [Harnessing Deep Learning and HPC Kernels via High-Level Loop and Tensor Abstractions on CPU Architectures](https://mlsanity.com/paper/2304.12576/) (2023)
- [Fast matrix multiplication for binary and ternary CNNs on ARM CPU](https://mlsanity.com/paper/2205.09120/) (2022)
- [Im2win: Memory Efficient Convolution On SIMD Architectures](https://mlsanity.com/paper/2306.14320/) (2023)
- [EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators](https://mlsanity.com/paper/2202.02310/) (2022)
- [Kernel-Segregated Transpose Convolution Operation](https://mlsanity.com/paper/2209.03704/) (2022)
- [High Performance Im2win and Direct Convolutions using Three Tensor Layouts on SIMD Architectures](https://mlsanity.com/paper/2408.00278/) (2024)
- [ConvBench: A Comprehensive Benchmark for 2D Convolution Primitive Evaluation](https://mlsanity.com/paper/2407.10730/) (2024)
- [GroupNL: Low-Resource and Robust CNN Design over Cloud and Device](https://mlsanity.com/paper/2506.12335/) (2025)
- [Benchmarking Deep Learning Convolutions on Energy-constrained CPUs](https://mlsanity.com/paper/2509.26217/) (2025)
- [Removing the Compute Bottleneck for Event-based Visual Place Recognition with Spiking Neural Networks](https://mlsanity.com/paper/2610.16022/) (2026)

## Abstract (arXiv)

Convolution layers are prevalent in many classes of deep neural networks, including Convolutional Neural Networks (CNNs) which provide state-of-the-art results for tasks like image recognition, neural machine translation and speech recognition. The computationally expensive nature of a convolution operation has led to the proliferation of implementations including matrix-matrix multiplication formulation, and direct convolution primarily targeting GPUs. In this paper, we introduce direct convolution kernels for x86 architectures, in particular for Xeon and XeonPhi systems, which are implemented via a dynamic compilation approach. Our JIT-based implementation shows close to theoretical peak performance, depending on the setting and the CPU architecture at hand. We additionally demonstrate how these JIT-optimized kernels can be integrated into a lightweight multi-node graph execution model. This illustrates that single- and multi-node runs yield high efficiencies and high image-throughputs when executing state-of-the-art image recognition tasks on CPUs.