# Standard Cell Library Design and Optimization Methodology for ASAP7 PDK

arXiv: https://arxiv.org/abs/1807.11396 · HTML: https://mlsanity.com/paper/1807.11396/

## Key facts

- Cited by 6 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 30 Jul 2018.

## Built on by (most cited first, 6 of 6)

- [LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models](https://mlsanity.com/paper/2201.08455/) (2022)
- [Differentiable Combinatorial Scheduling at Scale](https://mlsanity.com/paper/2406.06593/) (2024)
- [Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs](https://mlsanity.com/paper/2311.05722/) (2023)
- [A Benchmark on Directed Graph Representation Learning in Hardware Designs](https://mlsanity.com/paper/2410.06460/) (2024)
- [GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesis](https://mlsanity.com/paper/2511.18297/) (2025)
- [Differentiable Initialization-Accelerated CPU-GPU Hybrid Combinatorial Scheduling](https://mlsanity.com/paper/2603.28943/) (2026)

## Abstract (arXiv)

Standard cell libraries are the foundation for the entire backend design and optimization flow in modern application-specific integrated circuit designs. At 7nm technology node and beyond, standard cell library design and optimization is becoming increasingly difficult due to extremely complex design constraints, as described in the ASAP7 process design kit (PDK). Notable complexities include discrete transistor sizing due to FinFETs, complicated design rules from lithography and restrictive layout space from modern standard cell architectures. The design methodology presented in this paper enables efficient and high-quality standard cell library design and optimization with the ASAP7 PDK. The key techniques include exhaustive transistor sizing for cell timing optimization, transistor placement with generalized Euler paths and back-end design prototyping for library-level explorations.