# On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

arXiv: https://arxiv.org/abs/1806.09679 · HTML: https://mlsanity.com/paper/1806.09679/

## Key facts

- Cited by 9 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 14 Jun 2018.

## Built on by (most cited first, 9 of 9)

- [A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks](https://mlsanity.com/paper/2305.05750/) (2023)
- [A Survey on Failure Analysis and Fault Injection in AI Systems](https://mlsanity.com/paper/2407.00125/) (2024)
- [Random and Adversarial Bit Error Robustness: Energy-Efficient and Secure DNN Accelerators](https://mlsanity.com/paper/2104.08323/) (2021)
- [R2F: A Remote Retraining Framework for AIoT Processors with Computing Errors](https://mlsanity.com/paper/2107.03096/) (2021)
- [Fault-Tolerant Deep Learning: A Hierarchical Perspective](https://mlsanity.com/paper/2204.01942/) (2022)
- [ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance](https://mlsanity.com/paper/2503.24053/) (2025)
- [Using Convolutional Neural Networks for fault analysis and alleviation in accelerator systems](https://mlsanity.com/paper/2112.02657/) (2021)
- [Long-Term and Short-Term Transistor Aging in Deep Neural Networks: Impact and Mitigation](https://mlsanity.com/paper/2606.04266/) (2026)
- [A Degradation-Tolerance Benchmark for Camera-Only End-to-End Driving](https://mlsanity.com/paper/2608.29005/) (2026)

## Abstract (arXiv)

Machine Learning (ML) is making a strong resurgence in tune with the massive generation of unstructured data which in turn requires massive computational resources. Due to the inherently compute- and power-intensive structure of Neural Networks (NNs), hardware accelerators emerge as a promising solution. However, with technology node scaling below 10nm, hardware accelerators become more susceptible to faults, which in turn can impact the NN accuracy. In this paper, we study the resilience aspects of Register-Transfer Level (RTL) model of NN accelerators, in particular, fault characterization and mitigation. By following a High-Level Synthesis (HLS) approach, first, we characterize the vulnerability of various components of RTL NN. We observed that the severity of faults depends on both i) application-level specifications, i.e., NN data (inputs, weights, or intermediate), NN layers, and NN activation functions, and ii) architectural-level specifications, i.e., data representation model and the parallelism degree of the underlying accelerator. Second, motivated by characterization results, we present a low-overhead fault mitigation technique that can efficiently correct bit flips, by 47.3% better than state-of-the-art methods.