# A Highly Parallel FPGA Implementation of Sparse Neural Network Training

arXiv: https://arxiv.org/abs/1806.01087 · HTML: https://mlsanity.com/paper/1806.01087/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 31 May 2018.

## Built on by (most cited first, 4 of 4)

- [Two Sparsities Are Better Than One: Unlocking the Performance Benefits of Sparse-Sparse Networks](https://mlsanity.com/paper/2112.13896/) (2021)
- [Dynamic Probabilistic Pruning: A general framework for hardware-constrained pruning at different granularities](https://mlsanity.com/paper/2105.12686/) (2021)
- [Multiplierless MP-Kernel Machine For Energy-efficient Edge Devices](https://mlsanity.com/paper/2106.01958/) (2021)
- [Ultrafast On-Chip Online Learning via Spline Locality in Kolmogorov-Arnold Networks](https://mlsanity.com/paper/2602.02056/) (2026)

## Abstract (arXiv)

We demonstrate an FPGA implementation of a parallel and reconfigurable architecture for sparse neural networks, capable of on-chip training and inference. The network connectivity uses pre-determined, structured sparsity to significantly reduce complexity by lowering memory and computational requirements. The architecture uses a notion of edge-processing, leading to efficient pipelining and parallelization. Moreover, the device can be reconfigured to trade off resource utilization with training time to fit networks and datasets of varying sizes. The combined effects of complexity reduction and easy reconfigurability enable significantly greater exploration of network hyperparameters and structures on-chip. As proof of concept, we show implementation results on an Artix-7 FPGA.