# Parallel Programming for FPGAs

arXiv: https://arxiv.org/abs/1805.03648 · HTML: https://mlsanity.com/paper/1805.03648/

## Key facts

- Cited by 9 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 9 May 2018.

## Built on by (most cited first, 9 of 9)

- [HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks](https://mlsanity.com/paper/2504.12268/) (2025)
- [Leveraging viscous Hamilton-Jacobi PDEs for uncertainty quantification in scientific machine learning](https://mlsanity.com/paper/2404.08809/) (2024)
- [HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond](https://mlsanity.com/paper/2405.00820/) (2024)
- [Optimizing High-Level Synthesis Designs with Retrieval-Augmented Large Language Models](https://mlsanity.com/paper/2410.07356/) (2024)
- [Neural network architectures using min-plus algebra for solving certain high dimensional optimal control problems and Hamilton-Jacobi PDEs](https://mlsanity.com/paper/2105.03336/) (2021)
- [Physics Community Needs, Tools, and Resources for Machine Learning](https://mlsanity.com/paper/2203.16255/) (2022)
- [Architectural Implications of Neural Network Inference for High Data-Rate, Low-Latency Scientific Applications](https://mlsanity.com/paper/2403.08980/) (2024)
- [Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation](https://mlsanity.com/paper/2601.19941/) (2026)
- [Compilation and Optimizations for Efficient Machine Learning on Embedded Systems](https://mlsanity.com/paper/2206.03326/) (2022)

## Abstract (arXiv)

This book focuses on the use of algorithmic high-level synthesis (HLS) to build application-specific FPGA systems. Our goal is to give the reader an appreciation of the process of creating an optimized hardware design using HLS. Although the details are, of necessity, different from parallel programming for multicore processors or GPUs, many of the fundamental concepts are similar. For example, designers must understand memory hierarchy and bandwidth, spatial and temporal locality of reference, parallelism, and tradeoffs between computation and storage. This book is a practical guide for anyone interested in building FPGA systems. In a university environment, it is appropriate for advanced undergraduate and graduate courses. At the same time, it is also useful for practicing system designers and embedded programmers. The book assumes the reader has a working knowledge of C/C++ and includes a significant amount of sample code. In addition, we assume familiarity with basic computer architecture concepts (pipelining, speedup, Amdahl's Law, etc.). A knowledge of the RTL-based FPGA design flow is helpful, although not required.