# LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection

arXiv: https://arxiv.org/abs/1804.11275 · HTML: https://mlsanity.com/paper/1804.11275/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 30 Apr 2018.

## Built on by (most cited first, 3 of 3)

- [Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks](https://mlsanity.com/paper/2107.08695/) (2021)
- [TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans](https://mlsanity.com/paper/2405.05590/) (2024)
- [LLA: Enhancing Security and Privacy for Generative Models with Logic-Locked Accelerators](https://mlsanity.com/paper/2512.22307/) (2025)

## Abstract (arXiv)

In this work, we propose LUT-Lock, a novel Look-Up-Table-based netlist obfuscation algorithm, for protecting the intellectual property that is mapped to an FPGA bitstream or an ASIC netlist. We, first, illustrate the effectiveness of several key features that make the LUT-based obfuscation more resilient against SAT attacks and then we embed the proposed key features into our proposed LUT-Lock algorithm. We illustrates that LUT-Lock maximizes the resiliency of the LUT-based obfuscation against SAT attacks by forcing a near exponential increase in the execution time of a SAT solver with respect to the number of obfuscated gates. Hence, by adopting LUT-Lock algorithm, SAT attack execution time could be made unreasonably long by increasing the number of utilized LUTs.