# XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks

arXiv: https://arxiv.org/abs/1803.05849 · HTML: https://mlsanity.com/paper/1803.05849/

## Key facts

- Cited by 5 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 5 Mar 2018.

## Built on by (most cited first, 5 of 5)

- [Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey](https://mlsanity.com/paper/2203.08737/) (2022)
- [COBRA: Algorithm-Architecture Co-optimized Binary Transformer Accelerator for Edge Inference](https://mlsanity.com/paper/2504.16269/) (2025)
- [A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells](https://mlsanity.com/paper/2104.01699/) (2021)
- [Cost-Driven Hardware-Software Co-Optimization of Machine Learning Pipelines](https://mlsanity.com/paper/2310.07940/) (2023)
- [PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator](https://mlsanity.com/paper/2601.19920/) (2026)

## Abstract (arXiv)

Deploying state-of-the-art CNNs requires power-hungry processors and off-chip memory. This precludes the implementation of CNNs in low-power embedded systems. Recent research shows CNNs sustain extreme quantization, binarizing their weights and intermediate feature maps, thereby saving 8-32x memory and collapsing energy-intensive sum-of-products into XNOR-and-popcount operations. We present XNORBIN, an accelerator for binary CNNs with computation tightly coupled to memory for aggressive data reuse. Implemented in UMC 65nm technology XNORBIN achieves an energy efficiency of 95 TOp/s/W and an area efficiency of 2.0 TOp/s/MGE at 0.8 V.