# Programmable Switch as a Parallel Computing Device

arXiv: https://arxiv.org/abs/1803.01491 · HTML: https://mlsanity.com/paper/1803.01491/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 5 Mar 2018.

## Built on by (most cited first, 4 of 4)

- [Egeria: Efficient DNN Training with Knowledge-Guided Layer Freezing](https://mlsanity.com/paper/2201.06227/) (2022)
- [Automatic Configuration for Optimal Communication Scheduling in DNN Training](https://mlsanity.com/paper/2112.13509/) (2021)
- [Efficient Data-Plane Memory Scheduling for In-Network Aggregation](https://mlsanity.com/paper/2201.06398/) (2022)
- [Accelerating MoE with Dynamic In-Switch Computing on Multi-GPUs](https://mlsanity.com/paper/2605.05607/) (2026)

## Abstract (arXiv)

Modern switches have packet processing capacity of up to multi-tera bits per second, and they are also becoming more and more programmable. We seek to understand whether the programmability can translate packet processing capacity to computational power for parallel computing applications. In this paper, we first develop a simple mathematical model to understand the costs and overheads of data plane computation. Then we validate the the performance benefits of offloading computation to network. Using experiments on real data center network, we finnd that offloading computation to the data plane results in up to 20x speed-up for a simple Map-Reduce application. Motivated by this, we propose a parallel programming framework, p4mr, to help users efficiently program multiple switches. We successfully build and test a prototype of p4mr on a simulated testbed.