# Input-Aware Auto-Tuning of Compute-Bound HPC Kernels

arXiv: https://arxiv.org/abs/1802.05371 · HTML: https://mlsanity.com/paper/1802.05371/

## Key facts

- Cited by 5 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 15 Feb 2018.

## Built on by (most cited first, 5 of 5)

- [CATS: Contextually-Aware Thresholding for Sparsity in Large Language Models](https://mlsanity.com/paper/2404.08763/) (2024)
- [MGARD: A multigrid framework for high-performance, error-controlled data compression and refactoring](https://mlsanity.com/paper/2401.05994/) (2024)
- [Application Performance Modeling via Tensor Completion](https://mlsanity.com/paper/2210.10184/) (2022)
- [Using hardware performance counters to speed up autotuning convergence on GPUs](https://mlsanity.com/paper/2102.05297/) (2021)
- [Hardware-Aware Features for CUTLASS Kernel Selection](https://mlsanity.com/paper/2609.35587/) (2026)

## Abstract (arXiv)

Efficient implementations of HPC applications for parallel architectures generally rely on external software packages (e.g., BLAS, LAPACK, CUDNN). While these libraries provide highly optimized routines for certain characteristics of inputs (e.g., square matrices), they generally do not retain optimal performance across the wide range of problems encountered in practice. In this paper, we present an input-aware auto-tuning framework for matrix multiplications and convolutions, ISAAC, which uses predictive modeling techniques to drive highly parameterized PTX code templates towards not only hardware-, but also application-specific kernels. Numerical experiments on the NVIDIA Maxwell and Pascal architectures show up to 3x performance gains over both cuBLAS and cuDNN after only a few hours of auto-tuning.