# A Survey of FPGA-Based Neural Network Accelerator

arXiv: https://arxiv.org/abs/1712.08934 · HTML: https://mlsanity.com/paper/1712.08934/

## Key facts

- Cited by 17 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 24 Dec 2017.

## Built on by (most cited first, 17 of 17)

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- [Hardware Synthesis of State-Space Equations; Application to FPGA Implementation of Shallow and Deep Neural Networks](https://mlsanity.com/paper/2105.07131/) (2021)
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## Abstract (arXiv)

Recent researches on neural network have shown significant advantage in machine learning over traditional algorithms based on handcrafted features and models. Neural network is now widely adopted in regions like image, speech and video recognition. But the high computation and storage complexity of neural network inference poses great difficulty on its application. CPU platforms are hard to offer enough computation capacity. GPU platforms are the first choice for neural network process because of its high computation capacity and easy to use development frameworks. On the other hand, FPGA-based neural network inference accelerator is becoming a research topic. With specifically designed hardware, FPGA is the next possible solution to surpass GPU in speed and energy efficiency. Various FPGA-based accelerator designs have been proposed with software and hardware optimization techniques to achieve high speed and energy efficiency. In this paper, we give an overview of previous work on neural network inference accelerators based on FPGA and summarize the main techniques used. An investigation from software to hardware, from circuit level to system level is carried out to complete analysis of FPGA-based neural network inference accelerator design and serves as a guide to future work.