# Chipmunk: A Systolically Scalable 0.9 mm2, 3.08 Gop/s/mW @ 1.2 mW Accelerator for Near-Sensor Recurrent Neural Network Inference

arXiv: https://arxiv.org/abs/1711.05734 · HTML: https://mlsanity.com/paper/1711.05734/

## Key facts

- Cited by 6 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 15 Nov 2017.

## Built on by (most cited first, 6 of 6)

- [RecLight: A Recurrent Neural Network Accelerator with Integrated Silicon Photonics](https://mlsanity.com/paper/2209.00084/) (2022)
- [Language Modeling on a SpiNNaker 2 Neuromorphic Chip](https://mlsanity.com/paper/2312.09084/) (2023)
- [Vau da muntanialas: Energy-efficient multi-die scalable acceleration of RNN inference](https://mlsanity.com/paper/2202.07462/) (2022)
- [MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent units](https://mlsanity.com/paper/2505.08599/) (2025)
- [A Low-Power Streaming Speech Enhancement Accelerator For Edge Devices](https://mlsanity.com/paper/2503.21335/) (2025)
- [Cross-Layer Co-Optimized LSTM Accelerator for Real-Time Gait Analysis](https://mlsanity.com/paper/2604.13543/) (2026)

## Abstract (arXiv)

Recurrent neural networks (RNNs) are state-of-the-art in voice awareness/understanding and speech recognition. On-device computation of RNNs on low-power mobile and wearable devices would be key to applications such as zero-latency voice-based human-machine interfaces. Here we present Chipmunk, a small (<1 mm2) hardware accelerator for Long-Short Term Memory RNNs in UMC 65 nm technology capable to operate at a measured peak efficiency up to 3.08 Gop/s/mW at 1.24 mW peak power. To implement big RNN models without incurring in huge memory transfer overhead, multiple Chipmunk engines can cooperate to form a single systolic array. In this way, the Chipmunk architecture in a 75 tiles configuration can achieve real-time phoneme extraction on a demanding RNN topology proposed by Graves et al., consuming less than 13 mW of average power.