# Evaluating Ising Processing Units with Integer Programming

arXiv: https://arxiv.org/abs/1707.00355 · HTML: https://mlsanity.com/paper/1707.00355/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 2 Jul 2017.

## Built on by (most cited first, 1 of 1)

- [Towards Practical Explainability with Cluster Descriptors](https://mlsanity.com/paper/2210.10662/) (2022)

## Abstract (arXiv)

The recent emergence of novel computational devices, such as adiabatic quantum computers, CMOS annealers, and optical parametric oscillators, present new opportunities for hybrid-optimization algorithms that are hardware accelerated by these devices. In this work, we propose the idea of an Ising processing unit as a computational abstraction for reasoning about these emerging devices. The challenges involved in using and benchmarking these devices are presented and commercial mixed integer programming solvers are proposed as a valuable tool for the validation of these disparate hardware platforms. The proposed validation methodology is demonstrated on a D-Wave 2X adiabatic quantum computer, one example of an Ising processing unit. The computational results demonstrate that the D-Wave hardware consistently produces high-quality solutions and suggests that as IPU technology matures it could become a valuable co-processor in hybrid-optimization algorithms.