# Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training

arXiv: https://arxiv.org/abs/1706.06620 · HTML: https://mlsanity.com/paper/1706.06620/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 20 Jun 2017.

## Built on by (most cited first, 3 of 3)

- [Thermodynamic Natural Gradient Descent](https://mlsanity.com/paper/2405.13817/) (2024)
- [C3PU: Cross-Coupling Capacitor Processing Unit Using Analog-Mixed Signal In-Memory Computing for AI Inference](https://mlsanity.com/paper/2110.05947/) (2021)
- [A temporally and spatially local spike-based backpropagation algorithm to enable training in hardware](https://mlsanity.com/paper/2207.09755/) (2022)

## Abstract (arXiv)

Recently we have shown that an architecture based on resistive processing unit (RPU) devices has potential to achieve significant acceleration in deep neural network (DNN) training compared to today's software-based DNN implementations running on CPU/GPU. However, currently available device candidates based on non-volatile memory technologies do not satisfy all the requirements to realize the RPU concept. Here, we propose an analog CMOS-based RPU design (CMOS RPU) which can store and process data locally and can be operated in a massively parallel manner. We analyze various properties of the CMOS RPU to evaluate the functionality and feasibility for acceleration of DNN training.