# Deep Convolutional Neural Network Inference with Floating-point Weights and Fixed-point Activations

arXiv: https://arxiv.org/abs/1703.03073 · HTML: https://mlsanity.com/paper/1703.03073/

## Key facts

- Cited by 7 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 8 Mar 2017.

## Built on by (most cited first, 7 of 7)

- [Enabling Binary Neural Network Training on the Edge](https://mlsanity.com/paper/2102.04270/) (2021)
- [A Comprehensive Review and a Taxonomy of Edge Machine Learning: Requirements, Paradigms, and Techniques](https://mlsanity.com/paper/2302.08571/) (2023)
- [Number Systems for Deep Neural Network Architectures: A Survey](https://mlsanity.com/paper/2307.05035/) (2023)
- [End-to-end Keyword Spotting using Neural Architecture Search and Quantization](https://mlsanity.com/paper/2104.06666/) (2021)
- [Multi-Task Network Pruning and Embedded Optimization for Real-time Deployment in ADAS](https://mlsanity.com/paper/2101.07831/) (2021)
- [Deep Neural Networks Based Weight Approximation and Computation Reuse for 2-D Image Classification](https://mlsanity.com/paper/2105.02954/) (2021)
- [KML: Using Machine Learning to Improve Storage Systems](https://mlsanity.com/paper/2111.11554/) (2021)

## Abstract (arXiv)

Deep convolutional neural network (CNN) inference requires significant amount of memory and computation, which limits its deployment on embedded devices. To alleviate these problems to some extent, prior research utilize low precision fixed-point numbers to represent the CNN weights and activations. However, the minimum required data precision of fixed-point weights varies across different networks and also across different layers of the same network. In this work, we propose using floating-point numbers for representing the weights and fixed-point numbers for representing the activations. We show that using floating-point representation for weights is more efficient than fixed-point representation for the same bit-width and demonstrate it on popular large-scale CNNs such as AlexNet, SqueezeNet, GoogLeNet and VGG-16. We also show that such a representation scheme enables compact hardware multiply-and-accumulate (MAC) unit design. Experimental results show that the proposed scheme reduces the weight storage by up to 36% and power consumption of the hardware multiplier by up to 50%.
