# Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System

arXiv: https://arxiv.org/abs/1703.01909 · HTML: https://mlsanity.com/paper/1703.01909/

## Key facts

- Cited by 19 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 6 Mar 2017.

## Built on by (most cited first, 19 of 19)

- [Brain-inspired computing: We need a master plan](https://mlsanity.com/paper/2104.14517/) (2021)
- [Sparse Spiking Gradient Descent](https://mlsanity.com/paper/2105.08810/) (2021)
- [High-performance deep spiking neural networks with 0.3 spikes per neuron](https://mlsanity.com/paper/2306.08744/) (2023)
- [The Yin-Yang dataset](https://mlsanity.com/paper/2102.08211/) (2021)
- [Differentiable graph-structured models for inverse design of lattice materials](https://mlsanity.com/paper/2304.05422/) (2023)
- [Unlocking the potential of two-point cells for energy-efficient and resilient training of deep nets](https://mlsanity.com/paper/2211.01950/) (2022)
- [Navigating Local Minima in Quantized Spiking Neural Networks](https://mlsanity.com/paper/2202.07221/) (2022)
- [Distributed Representations Enable Robust Multi-Timescale Symbolic Computation in Neuromorphic Hardware](https://mlsanity.com/paper/2405.01305/) (2024)
- [Effect of Batch Normalization on Noise Resistant Property of Deep Learning Models](https://mlsanity.com/paper/2205.07372/) (2022)
- [Towards Chip-in-the-loop Spiking Neural Network Training via Metropolis-Hastings Sampling](https://mlsanity.com/paper/2402.06284/) (2024)
- [Demonstrating Analog Inference on the BrainScaleS-2 Mobile System](https://mlsanity.com/paper/2103.15960/) (2021)
- [Memristor-Based Neural Network Accelerators for Space Applications: Enhancing Performance with Temporal Averaging and SIRENs](https://mlsanity.com/paper/2509.04506/) (2025)
- [Impact of Learning Rate on Noise Resistant Property of Deep Learning Models](https://mlsanity.com/paper/2205.07856/) (2022)
- [Exploring Tradeoffs in Spiking Neural Networks](https://mlsanity.com/paper/2212.09500/) (2022)
- [Efficient Spatio-Temporal Signal Recognition on Edge Devices Using PointLCA-Net](https://mlsanity.com/paper/2411.14585/) (2024)
- [DarwinWafer: A Wafer-Scale Neuromorphic Chip](https://mlsanity.com/paper/2509.16213/) (2025)
- [Learning Long-Range Dependencies with Temporal Predictive Coding](https://mlsanity.com/paper/2602.18131/) (2026)
- [A Synthesizable RTL Implementation of Predictive Coding Networks](https://mlsanity.com/paper/2603.18066/) (2026)
- [The SpiNNaker2 chip: a many-core platform for flexible and scalable brain-inspired computing](https://mlsanity.com/paper/2607.24396/) (2026)

## Abstract (arXiv)

Emulating spiking neural networks on analog neuromorphic hardware offers several advantages over simulating them on conventional computers, particularly in terms of speed and energy consumption. However, this usually comes at the cost of reduced control over the dynamics of the emulated networks. In this paper, we demonstrate how iterative training of a hardware-emulated network can compensate for anomalies induced by the analog substrate. We first convert a deep neural network trained in software to a spiking network on the BrainScaleS wafer-scale neuromorphic system, thereby enabling an acceleration factor of 10 000 compared to the biological time domain. This mapping is followed by the in-the-loop training, where in each training step, the network activity is first recorded in hardware and then used to compute the parameter updates in software via backpropagation. An essential finding is that the parameter updates do not have to be precise, but only need to approximately follow the correct gradient, which simplifies the computation of updates. Using this approach, after only several tens of iterations, the spiking network shows an accuracy close to the ideal software-emulated prototype. The presented techniques show that deep spiking networks emulated on analog neuromorphic devices can attain good computational performance despite the inherent variations of the analog substrate.