# FPMax: a 106GFLOPS/W at 217GFLOPS/mm2 Single-Precision FPU, and a 43.7GFLOPS/W at 74.6GFLOPS/mm2 Double-Precision FPU, in 28nm UTBB FDSOI

arXiv: https://arxiv.org/abs/1606.07852 · HTML: https://mlsanity.com/paper/1606.07852/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 24 Jun 2016.

## Built on by (most cited first, 1 of 1)

- [KAN-SAs: Efficient Acceleration of Kolmogorov-Arnold Networks on Systolic Arrays](https://mlsanity.com/paper/2512.00055/) (2025)

## Abstract (arXiv)

FPMax implements four FPUs optimized for latency or throughput workloads in two precisions, fabricated in 28nm UTBB FDSOI. Each unit's parameters, e.g pipeline stages, booth encoding etc., were optimized to yield 1.42ns latency at 110GLOPS/W (SP) and 1.39ns latency at 36GFLOPS/W (DP). At 100% activity, body-bias control improves the energy efficiency by about 20%; at 10% activity this saving is almost 2x. Keywords: FPU, energy efficiency, hardware generator, SOI