# DLAU: A Scalable Deep Learning Accelerator Unit on FPGA

arXiv: https://arxiv.org/abs/1605.06894 · HTML: https://mlsanity.com/paper/1605.06894/

## Key facts

- Cited by 12 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 23 May 2016.

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- [The Feasibility of Implementing Large-Scale Transformers on Multi-FPGA Platforms](https://mlsanity.com/paper/2404.16158/) (2024)
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## Abstract (arXiv)

As the emerging field of machine learning, deep learning shows excellent ability in solving complex learning problems. However, the size of the networks becomes increasingly large scale due to the demands of the practical applications, which poses significant challenge to construct a high performance implementations of deep learning neural networks. In order to improve the performance as well to maintain the low power cost, in this paper we design DLAU, which is a scalable accelerator architecture for large-scale deep learning networks using FPGA as the hardware prototype. The DLAU accelerator employs three pipelined processing units to improve the throughput and utilizes tile techniques to explore locality for deep learning applications. Experimental results on the state-of-the-art Xilinx FPGA board demonstrate that the DLAU accelerator is able to achieve up to 36.1x speedup comparing to the Intel Core2 processors, with the power consumption at 234mW.