# A 128 channel Extreme Learning Machine based Neural Decoder for Brain Machine Interfaces

arXiv: https://arxiv.org/abs/1509.07450 · HTML: https://mlsanity.com/paper/1509.07450/

## Key facts

- Cited by 8 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 22 Sep 2015.

## Built on by (most cited first, 8 of 8)

- [Challenges and Opportunities of Edge AI for Next-Generation Implantable BMIs](https://mlsanity.com/paper/2204.02362/) (2022)
- [Intelligent and Miniaturized Neural Interfaces: An Emerging Era in Neurotechnology](https://mlsanity.com/paper/2405.10780/) (2024)
- [LLMs Help Alleviate the Cross-Subject Variability in Brain Signal and Language Alignment](https://mlsanity.com/paper/2501.02621/) (2025)
- [Combining SNNs with Filtering for Efficient Neural Decoding in Implantable Brain-Machine Interfaces](https://mlsanity.com/paper/2312.15889/) (2023)
- [A survey on the development status and application prospects of knowledge graph in smart grids](https://mlsanity.com/paper/2211.00901/) (2022)
- [Towards On-Device Learning and Reconfigurable Hardware Implementation for Encoded Single-Photon Signal Processing](https://mlsanity.com/paper/2504.09028/) (2025)
- [Machine-Learning-Powered Neural Interfaces for Smart Prosthetics and Diagnostics](https://mlsanity.com/paper/2505.02516/) (2025)
- [Architectural Exploration of Hybrid Neural Decoders for Neuromorphic Implantable BMI](https://mlsanity.com/paper/2505.05983/) (2025)

## Abstract (arXiv)

Currently, state-of-the-art motor intention decoding algorithms in brain-machine interfaces are mostly implemented on a PC and consume significant amount of power. A machine learning co-processor in 0.35um CMOS for motor intention decoding in brain-machine interfaces is presented in this paper. Using Extreme Learning Machine algorithm and low-power analog processing, it achieves an energy efficiency of 290 GMACs/W at a classification rate of 50 Hz. The learning in second stage and corresponding digitally stored coefficients are used to increase robustness of the core analog processor. The chip is verified with neural data recorded in monkey finger movements experiment, achieving a decoding accuracy of 99.3% for movement type. The same co-processor is also used to decode time of movement from asynchronous neural spikes. With time-delayed feature dimension enhancement, the classification accuracy can be increased by 5% with limited number of input channels. Further, a sparsity promoting training scheme enables reduction of number of programmable weights by ~2X.