# Robust and Efficient Elimination of Cache and Timing Side Channels

arXiv: https://arxiv.org/abs/1506.00189 · HTML: https://mlsanity.com/paper/1506.00189/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 31 May 2015.

## Built on by (most cited first, 1 of 1)

- [Automated Side Channel Analysis of Media Software with Manifold Learning](https://mlsanity.com/paper/2112.04947/) (2021)

## Abstract (arXiv)

Timing and cache side channels provide powerful attacks against many sensitive operations including cryptographic implementations. Existing defenses cannot protect against all classes of such attacks without incurring prohibitive performance overhead. A popular strategy for defending against all classes of these attacks is to modify the implementation so that the timing and cache access patterns of every hardware instruction is independent of the secret inputs. However, this solution is architecture-specific, brittle, and difficult to get right. In this paper, we propose and evaluate a robust low-overhead technique for mitigating timing and cache channels. Our solution requires only minimal source code changes and works across multiple languages/platforms. We report the experimental results of applying our solution to protect several C, C++, and Java programs. Our results demonstrate that our solution successfully eliminates the timing and cache side-channel leaks while incurring significantly lower performance overhead than existing approaches.