# Holographic Graph Neuron: a Bio-Inspired Architecture for Pattern Processing

arXiv: https://arxiv.org/abs/1501.03784 · HTML: https://mlsanity.com/paper/1501.03784/

## Key facts

- Cited by 10 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 15 Jan 2015.

## Built on by (most cited first, 10 of 10)

- [A Survey on Hyperdimensional Computing aka Vector Symbolic Architectures, Part I: Models and Data Transformations](https://mlsanity.com/paper/2111.06077/) (2021)
- [Understanding Hyperdimensional Computing for Parallel Single-Pass Learning](https://mlsanity.com/paper/2202.04805/) (2022)
- [Learning from Hypervectors: A Survey on Hypervector Encoding](https://mlsanity.com/paper/2308.00685/) (2023)
- [An Encoding Framework for Binarized Images using HyperDimensional Computing](https://mlsanity.com/paper/2312.00454/) (2023)
- [Shift-Equivariant Similarity-Preserving Hypervector Representations of Sequences](https://mlsanity.com/paper/2112.15475/) (2021)
- [Laplace-HDC: Understanding the geometry of binary hyperdimensional computing](https://mlsanity.com/paper/2404.10759/) (2024)
- [Recursive Binding for Similarity-Preserving Hypervector Representations of Sequences](https://mlsanity.com/paper/2201.11691/) (2022)
- [The Hyperdimensional Transform for Distributional Modelling, Regression and Classification](https://mlsanity.com/paper/2311.08150/) (2023)
- [HD-CB: The First Exploration of Hyperdimensional Computing for Contextual Bandits Problems](https://mlsanity.com/paper/2501.16863/) (2025)
- [Robust Clustering using Hyperdimensional Computing](https://mlsanity.com/paper/2312.02407/) (2023)

## Abstract (arXiv)

This article proposes the use of Vector Symbolic Architectures for implementing Hierarchical Graph Neuron, an architecture for memorizing patterns of generic sensor stimuli. The adoption of a Vector Symbolic representation ensures a one-layered design for the approach, while maintaining the previously reported properties and performance characteristics of Hierarchical Graph Neuron, and also improving the noise resistance of the architecture. The proposed architecture enables a linear (with respect to the number of stored entries) time search for an arbitrary sub-pattern.