# Lithography Hotspot Detection and Mitigation in Nanometer VLSI

arXiv: https://arxiv.org/abs/1402.3150 · HTML: https://mlsanity.com/paper/1402.3150/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 13 Feb 2014.

## Built on by (most cited first, 2 of 2)

- [A Physics-Constrained, Design-Driven Methodology for Defect Dataset Generation in Optical Lithography](https://mlsanity.com/paper/2512.09001/) (2025)
- [Improving Routability Prediction via NAS Using a Smooth One-shot Augmented Predictor](https://mlsanity.com/paper/2411.14296/) (2024)

## Abstract (arXiv)

With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithography hotspots is important at both physical verification and early physical design stages. While detailed lithography simulations can be very accurate, they may be too computationally expensive for full-chip scale and physical design inner loops. Meanwhile, pattern matching and machine learning based hotspot detection methods can provide acceptable quality and yet fast turn-around-time for full-chip scale physical verification and design. In this paper, we discuss some key issues and recent results on lithography hotspot detection and mitigation in nanometer VLSI.