# A High-Performance Triple Patterning Layout Decomposer with Balanced Density

arXiv: https://arxiv.org/abs/1402.2890 · HTML: https://mlsanity.com/paper/1402.2890/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 12 Feb 2014.

## Built on by (most cited first, 1 of 1)

- [GPU-accelerated Matrix Cover Algorithm for Multiple Patterning Layout Decomposition](https://mlsanity.com/paper/2303.14335/) (2023)

## Abstract (arXiv)

Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high performance layout decomposer for TPL. Density balancing is seamlessly integrated into all key steps in our TPL layout decomposition, including density-balanced semi-definite programming (SDP), density-based mapping, and density-balanced graph simplification. Our new TPL decomposer can obtain high performance even compared to previous state-of-the-art layout decomposers which are not balanced-density aware, e.g., by Yu et al. (ICCAD'11), Fang et al. (DAC'12), and Kuang et al. (DAC'13). Furthermore, the balanced-density version of our decomposer can provide more balanced density which leads to less edge placement error (EPE), while the conflict and stitch numbers are still very comparable to our non-balanced-density baseline.