# Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting

arXiv: https://arxiv.org/abs/1402.2425 · HTML: https://mlsanity.com/paper/1402.2425/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 11 Feb 2014.

## Built on by (most cited first, 1 of 1)

- [GPU-accelerated Matrix Cover Algorithm for Multiple Patterning Layout Decomposition](https://mlsanity.com/paper/2303.14335/) (2023)

## Abstract (arXiv)

Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently LELEEC process was proposed to overcome the limitations, where the third mask is used to generate the end-cuts. In this paper we propose the first study for LELEEC layout decomposition. Conflict graphs and end-cut graphs are constructed to extract all the geometrical relationships of input layout and end-cut candidates. Based on these graphs, integer linear programming (ILP) is formulated to minimize the conflict number and the stitch number.