# Counter-Strategy Guided Refinement of GR(1) Temporal Logic Specifications

arXiv: https://arxiv.org/abs/1308.4113 · HTML: https://mlsanity.com/paper/1308.4113/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 19 Aug 2013.

## Built on by (most cited first, 2 of 2)

- [Traffic-Rule-Compliant Trajectory Repair via Satisfiability Modulo Theories and Reachability Analysis](https://mlsanity.com/paper/2412.15837/) (2024)
- [INPROVF: Leveraging Large Language Models to Repair High-level Robot Controllers from Assumption Violations](https://mlsanity.com/paper/2503.13660/) (2025)

## Abstract (arXiv)

The reactive synthesis problem is to find a finite-state controller that satisfies a given temporal-logic specification regardless of how its environment behaves. Developing a formal specification is a challenging and tedious task and initial specifications are often unrealizable. In many cases, the source of unrealizability is the lack of adequate assumptions on the environment of the system. In this paper, we consider the problem of automatically correcting an unrealizable specification given in the generalized reactivity (1) fragment of linear temporal logic by adding assumptions on the environment. When a temporal-logic specification is unrealizable, the synthesis algorithm computes a counter-strategy as a witness. Our algorithm then analyzes this counter-strategy and synthesizes a set of candidate environment assumptions that can be used to remove the counter-strategy from the environment's possible behaviors. We demonstrate the applicability of our approach with several case studies.