# A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

arXiv: https://arxiv.org/abs/1305.0185 · HTML: https://mlsanity.com/paper/1305.0185/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 1 May 2013.

## Built on by (most cited first, 1 of 1)

- [An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes](https://mlsanity.com/paper/2107.03688/) (2021)

## Abstract (arXiv)

This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10-13 at a bit-energy-to-noise-power-spectral-density ratio (Eb/N0) of 3.55 dB.