{"list":"other","total":108,"rows":[{"id":"1706.03762","title":"Attention Is All You Need","created":"2017-06-12","cited_by_count":60361},{"id":"2005.14165","title":"Language Models are Few-Shot Learners","created":"2020-05-28","cited_by_count":32419},{"id":"2407.21783","title":"The Llama 3 Herd of Models","created":"2024-07-31","cited_by_count":14715},{"id":"2302.13971","title":"LLaMA: Open and Efficient Foundation Language Models","created":"2023-02-27","cited_by_count":14132},{"id":"2107.03374","title":"Evaluating Large Language Models Trained on Code","created":"2021-07-07","cited_by_count":8320},{"id":"2304.08485","title":"Visual Instruction Tuning","created":"2023-04-17","cited_by_count":7869},{"id":"2501.12948","title":"DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning","created":"2025-01-22","cited_by_count":6330},{"id":"2204.05862","title":"Training a Helpful and Harmless Assistant with Reinforcement Learning from Human Feedback","created":"2022-04-12","cited_by_count":3720},{"id":"2310.06770","title":"SWE-bench: Can Language Models Resolve Real-World GitHub Issues?","created":"2023-10-10","cited_by_count":3373},{"id":"2309.16609","title":"Qwen Technical Report","created":"2023-09-28","cited_by_count":3344},{"id":"2409.12186","title":"Qwen2.5-Coder Technical Report","created":"2024-09-18","cited_by_count":1203},{"id":"2401.14196","title":"DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence","created":"2024-01-25","cited_by_count":1181},{"id":"2203.13474","title":"CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesis","created":"2022-03-25","cited_by_count":885},{"id":"2305.06161","title":"StarCoder: may the source be with you!","created":"2023-05-09","cited_by_count":799},{"id":"2406.00515","title":"A Survey on Large Language Models for Code Generation","created":"2024-06-01","cited_by_count":658},{"id":"2401.02954","title":"DeepSeek LLM: Scaling Open-Source Language Models with Longtermism","created":"2024-01-05","cited_by_count":642},{"id":"2306.11644","title":"Textbooks Are All You Need","created":"2023-06-20","cited_by_count":569},{"id":"2309.05463","title":"Textbooks Are All You Need II: phi-1.5 technical report","created":"2023-09-11","cited_by_count":565},{"id":"2406.15877","title":"BigCodeBench: Benchmarking Code Generation with Diverse Function Calls and Complex Instructions","created":"2024-06-22","cited_by_count":546},{"id":"2402.19173","title":"StarCoder 2 and The Stack v2: The Next Generation","created":"2024-02-29","cited_by_count":502},{"id":"2308.10620","title":"Large Language Models for Software Engineering: A Systematic Literature Review","created":"2023-08-21","cited_by_count":399},{"id":"2305.07922","title":"CodeT5+: Open Code Large Language Models for Code Understanding and Generation","created":"2023-05-13","cited_by_count":333},{"id":"2309.07544","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","created":"2023-09-14","cited_by_count":252},{"id":"2308.00708","title":"VeriGen: A Large Language Model for Verilog Code Generation","created":"2023-07-28","cited_by_count":200},{"id":"2406.11409","title":"CodeGemma: Open Code Models Based on Gemma","created":"2024-06-17","cited_by_count":150},{"id":"2308.05345","title":"RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model","created":"2023-08-10","cited_by_count":148},{"id":"2406.11704","title":"Nemotron-4 340B Technical Report","created":"2024-06-17","cited_by_count":144},{"id":"2305.02309","title":"CodeGen2: Lessons for Training LLMs on Programming and Natural Languages","created":"2023-05-03","cited_by_count":125},{"id":"2212.11140","title":"Benchmarking Large Language Models for Automated Verilog RTL Code Generation","created":"2022-12-13","cited_by_count":115},{"id":"2305.14019","title":"ChipGPT: How far are we from natural language hardware design","created":"2023-05-23","cited_by_count":105},{"id":"2311.16543","title":"RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models","created":"2023-11-28","cited_by_count":100},{"id":"2402.03375","title":"BetterV: Controlled Verilog Generation with Discriminative Guidance","created":"2024-02-03","cited_by_count":100},{"id":"2402.16694","title":"HumanEval-XL: A Multilingual Code Generation Benchmark for Cross-lingual Natural Language Generalization","created":"2024-02-26","cited_by_count":86},{"id":"2408.08927","title":"VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool","created":"2024-08-15","cited_by_count":85},{"id":"2311.04887","title":"AutoChip: Automating HDL Generation Using LLM Feedback","created":"2023-11-08","cited_by_count":83},{"id":"2312.08617","title":"RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution","created":"2023-12-14","cited_by_count":71},{"id":"2410.03981","title":"A Survey on LLM-based Code Generation for Low-Resource and Domain-Specific Programming Languages","created":"2024-10-04","cited_by_count":66},{"id":"2407.16237","title":"OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection","created":"2024-07-23","cited_by_count":56},{"id":"2009.01026","title":"DAVE: Deriving Automatically Verilog from English","created":"2020-08-27","cited_by_count":48},{"id":"2408.11053","title":"Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation","created":"2024-08-20","cited_by_count":45},{"id":"2404.06369","title":"WebCode2M: A Real-World Dataset for Code Generation from Webpage Designs","created":"2024-04-09","cited_by_count":44},{"id":"2506.14074","title":"Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification","created":"2025-06-17","cited_by_count":44},{"id":"2402.03289","title":"Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS","created":"2024-02-05","cited_by_count":43},{"id":"2409.12993","title":"CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair","created":"2024-09-19","cited_by_count":42},{"id":"2406.00115","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","created":"2024-05-31","cited_by_count":39},{"id":"2407.10424","title":"CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization","created":"2024-07-15","cited_by_count":38},{"id":"2403.11202","title":"Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework","created":"2024-03-17","cited_by_count":36},{"id":"2407.18333","title":"AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs","created":"2024-07-21","cited_by_count":36},{"id":"2505.24183","title":"QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation","created":"2025-05-30","cited_by_count":35},{"id":"2412.07822","title":"MAGE: A Multi-Agent Engine for Automated RTL Code Generation","created":"2024-12-10","cited_by_count":31},{"id":"2503.15112","title":"OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation","created":"2025-03-19","cited_by_count":31},{"id":"2405.17378","title":"RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects","created":"2024-05-27","cited_by_count":26},{"id":"2501.04908","title":"HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers","created":"2025-01-09","cited_by_count":25},{"id":"2407.18276","title":"Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design","created":"2024-07-23","cited_by_count":24},{"id":"2502.15832","title":"DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model","created":"2025-02-20","cited_by_count":23},{"id":"2506.05566","title":"ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation","created":"2025-06-05","cited_by_count":22},{"id":"2502.18297","title":"DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis","created":"2025-02-25","cited_by_count":21},{"id":"2404.08806","title":"CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation","created":"2024-04-12","cited_by_count":19},{"id":"2411.11856","title":"Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback","created":"2024-11-01","cited_by_count":19},{"id":"2412.06947","title":"PyraNet: A Multi-Layered Hierarchical Dataset for Verilog","created":"2024-12-09","cited_by_count":19},{"id":"2504.03723","title":"VFlow: Discovering Optimal Agentic Workflows for Verilog Generation","created":"2025-03-30","cited_by_count":19},{"id":"2505.13479","title":"RTL++: Graph-enhanced LLM for RTL Code Generation","created":"2025-05-11","cited_by_count":18},{"id":"2503.16528","title":"HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL","created":"2025-03-18","cited_by_count":17},{"id":"2504.03711","title":"A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA","created":"2025-03-28","cited_by_count":17},{"id":"2505.08903","title":"Assessing and Advancing Benchmarks for Evaluating Large Language Models in Software Engineering Tasks","created":"2025-05-13","cited_by_count":17},{"id":"2505.11849","title":"VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation","created":"2025-05-17","cited_by_count":16},{"id":"2404.08029","title":"A Multi-Expert Large Language Model Architecture for Verilog Code Generation","created":"2024-04-11","cited_by_count":15},{"id":"2407.18271","title":"Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning","created":"2024-07-21","cited_by_count":15},{"id":"2409.11411","title":"AIvril: AI-Driven RTL Generation With Verification In-The-Loop","created":"2024-09-03","cited_by_count":15},{"id":"2411.17569","title":"RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation","created":"2024-11-26","cited_by_count":15},{"id":"2504.15804","title":"Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback","created":"2025-04-22","cited_by_count":14},{"id":"2507.16200","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","created":"2025-07-22","cited_by_count":14},{"id":"2412.05393","title":"HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design","created":"2024-12-06","cited_by_count":13},{"id":"2504.15659","title":"VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation","created":"2025-04-22","cited_by_count":13},{"id":"2403.07257","title":"The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models","created":"2024-03-12","cited_by_count":12},{"id":"2503.13572","title":"VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination","created":"2025-03-17","cited_by_count":12},{"id":"2503.16514","title":"VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric","created":"2025-03-15","cited_by_count":12},{"id":"2504.14560","title":"ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model","created":"2025-04-20","cited_by_count":12},{"id":"2407.08473","title":"Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation","created":"2024-07-11","cited_by_count":11},{"id":"2502.00028","title":"VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency","created":"2025-01-22","cited_by_count":11},{"id":"2304.13840","title":"A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation","created":"2023-04-26","cited_by_count":10},{"id":"2402.01728","title":"Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge","created":"2024-01-27","cited_by_count":10},{"id":"2506.15697","title":"DeepRTL2: A Versatile Model for RTL-Related Tasks","created":"2025-05-28","cited_by_count":10},{"id":"2407.12022","title":"ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generation","created":"2024-06-28","cited_by_count":9},{"id":"2412.11014","title":"CoopetitiveV: Leveraging LLM-powered Coopetitive Multi-Agent Prompting for High-quality Verilog Generation","created":"2024-12-15","cited_by_count":9},{"id":"2501.05470","title":"RTLSquad: Multi-Agent Based Interpretable RTL Design","created":"2025-01-06","cited_by_count":9},{"id":"2405.02326","title":"Evaluating LLMs for Hardware Design and Test","created":"2024-04-23","cited_by_count":8},{"id":"2507.13369","title":"VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation","created":"2025-07-09","cited_by_count":8},{"id":"2508.05266","title":"Understanding and Mitigating Errors of LLM-Generated RTL Code","created":"2025-08-07","cited_by_count":8},{"id":"2411.03471","title":"MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs","created":"2024-11-05","cited_by_count":7},{"id":"2504.08862","title":"RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentation","created":"2025-04-11","cited_by_count":7},{"id":"2506.00005","title":"Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form","created":"2025-05-07","cited_by_count":7},{"id":"2501.12702","title":"Paradigm-Based Automatic HDL Code Generation Using LLMs","created":"2025-01-22","cited_by_count":6},{"id":"2505.15873","title":"Abstractions-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design","created":"2025-05-21","cited_by_count":6},{"id":"2506.15066","title":"ChatModel: Automating Reference Model Design and Verification with LLMs","created":"2025-06-18","cited_by_count":6},{"id":"2508.06047","title":"ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis","created":"2025-08-08","cited_by_count":6},{"id":"2502.19091","title":"Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation","created":"2025-02-26","cited_by_count":5},{"id":"2507.02226","title":"DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs","created":"2025-07-03","cited_by_count":5},{"id":"2403.07039","title":"From English to ASIC: Hardware Implementation with Large Language Model","created":"2024-03-11","cited_by_count":3},{"id":"2501.02446","title":"RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework","created":"2025-01-05","cited_by_count":3}],"next_cursor":"100"}